參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 144/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
P
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M59
M58
M55
M57
M56
M54
M53
CLKX
FSX
DX
DR
M62
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 5-43. ASP as SPI Timing Requirements
CLKSTP = 11b, CLKXP = 1 (see
Figure 5-45
)
MASTER
MIN
11
0
NO.
UNIT
MAX
M58
M59
t
su(DRV-CKXL)
t
h(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
ns
ns
Table 5-44. ASP as SPI Switching Characteristics
(1)(2)
CLKSTP = 11b, CLKXP = 1 (see
Figure 5-45
)
MASTER
MIN
38.5 or
2P
(3)(3)
H
1
– 1
T – 2
–2
NO.
PARAMETER
UNIT
MAX
M62
tc(CKX)
Cycle time, CLKX
ns
M53
M54
M55
t
d(CKXH-FXH)
t
d(FXL-CKXL)
t
d(CKXL-DXV)
Delay time, CLKX high to FSX high
(4)
Delay time, FSX low to CLKX low
(5)
Delay time, CLKX low to DX valid
Disable time, DX high impedance following last data bit from
CLKX high
Delay time, FSX low to DX valid
H
1
+ 3
T + 2
ns
ns
ns
6
M56
t
dis(CKXH-DXHZ)
– 3
+ 3
ns
M57
t
d(FXL-DXV)
L
1
– 1
L
1
+ 10
ns
(1)
(2)
P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see
Section 3.5
) .
T = CLKX period = (1 + CLKGDV)
×
2P
L
1
= CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2)
×
2P when CLKGDV is even
H
1
= CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1)
×
2P when CLKGDV is even
Use which ever value is greater.
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
(3)
(4)
(5)
Figure 5-45. ASP as SPI: CLKSTP = 11b, CLKXP = 1
144
DM355 Peripheral Information and Electrical Specifications
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