參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 101/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
P
5.5.3
Clock PLL Electrical Data/Timing (Input and Output Clocks)
MXI/CLKIN
2
3
4
4
5
1
MXI/CLKIN
2
3
4
4
5
1
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 5-5. Timing Requirements for MXI1/CLKIN1
(1)(2)
(see
Figure 5-7
)
DM355
TYP
NO
.
UNIT
MIN
MAX
41.6
(3)
0.55C
0.55C
0.05C
0.02C
1
2
3
4
5
t
c(MXI1)
t
w(MXI1H)
t
w(MXI1L)
t
t(MXI1)
t
J(MXI1)
Cycle time, MXI1/CLKIN1
Pulse duration, MXI1/CLKIN1 high
Pulse duration, MXI1/CLKIN1 low
Transition time, MXI1/CLKIN1
Period jitter, MXI1/CLKIN1
27.7
(3)
0.45C
0.45C
ns
ns
ns
ns
ns
(1)
(2)
(3)
The reference points for the rise and fall transitions are measured at V
MAX and V
MIN.
C = MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns.
tc(MXI1) = 41.6 ns and tc(MXI1) = 27.7 ns are the only supported cycle times for MXI1/CLKIN1.
Figure 5-7. MXI1/CLKIN1 Timing
Table 5-6. Timing Requirements for MXI2/CLKIN2
(1)(2)
(see
Figure 5-7
)
NO.
DM355
UNIT
MIN
TYP
MAX
1
2
3
4
5
t
c(MXI2)
t
w(MXI2H)
t
w(MXI2L)
t
t(MXI2)
t
J(MXI2)
Cycle time, MXI2/CLKIN2
Pulse duration, MXI2/CLKIN2 high
Pulse duration, MXI2/CLKIN2 low
Transition time, MXI2/CLKIN2
Period jitter, MXI2/CLKIN2
37.037
(3)
0.45C
0.45C
37.037
(3)
0.55C
0.55C
0.05C
0.02C
ns
ns
ns
ns
ns
(1)
(2)
(3)
The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
C = MXI2/CLKIN2 cycle time in ns. For example, when MXI2/CLKIN2 frequency is 27 MHz use C = 37.037 ns.
tc(MXI2) = 37.037 ns is the only supported cycle time for MXI2/CLKIN2.
Figure 5-8. MXI2/CLKIN2 Timing
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DM355 Peripheral Information and Electrical Specifications
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