參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 139/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
P
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP
(1)(2)
(see
Figure 5-41
)
DM355
MIN
NO.
PARAMETER
UNIT
MAX
2
17
3
t
c(CKRX)
td(CLKS-CLKRX)
t
w(CKRX)
Cycle time, CLKR/X
Delay time, CLKS high to internal CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
38.5 or 2P
(3)(4)(5)
ns
1
24
C - 1
(6)
C + 1
(6)
ns
3
3
25
25
4
t
d(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
ns
-4
3
8
9
t
d(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
ns
25
12
12
12
25
14
ns
ns
ns
ns
tdis(CKXH-
DXHZ)
Disable time, DX high impedance following last data
bit from CLKX high
12
-5
3
13
t
d(CKXH-DXV)
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
14
t
d(FXH-DXV)
ns
FSX ext
25
(1)
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
Minimum delay times also represent minimum output hold times.
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see
Section 3.5
) .
Use which ever value is greater.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/SYSCLK2, where SYSCLK2 is an output of PLLC1 (see
Section 3.5
) )
S = sample rate generator input clock = CLKS if CLKSM = 0
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the ASP bit rate
does not
exceed the maximum limit (see footnote (3) above).
(2)
(3)
(4)
(5)
(6)
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DM355 Peripheral Information and Electrical Specifications
139
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