參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 152/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
P
6
Revision History (Revision B)
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
This data sheet revision history highlights the technical changes made to the SPRS463
A
device-specific
data sheet to make it an SPRS463
B
revision.
Note:
The "A" revision history table is also included in this document (see next page) because the
SPRS463A document has not been available for a long enough period of time to allow user's to digest the
revision history updates.
ADDS/CHANGES/DELETES
Global: Updated/Changed "V
SA_PLL1
"
to
"V
SSA_PLL1
"
Global: Updated/Changed "MX
1
2"
to
"MX
I
2"
Global: Updated/Changed the signal
from
"DDR_GATE0"
to
"DDR_
DQ
GATE0" and the associated pin descriptions
Global: Updated/Changed the signal
from
"DDR_GATE1"
to
"DDR_
DQ
GATE1" and the associated pin descriptions
Section 1.1
, Features:
Video Processing Subsystem feature:
–
14-Bit Parallel AFE (Analog Front End) Interface Up to
67.5 MHz
:
Updated/Changed speed
from
67.5 MHz
to
75 MHz
Section 1.3
, Functional Block Diagram:
Updated/Changed "3A"
to
"H3A"
Updated/Changed "(EMIF2.3)"
to
"(AEMIF)"
Section 2.4.7
, Universal Serial Bus (USB) Interface:
Table 2-13
, USB Terminal Functions:
Updated/Changed the V
SS_USB_REF
description
Section 2.5
, Pin List:
Table 2-23
, DM355 Pin Descriptions:
Updated/Changed the V
SS_USB_REF
description
Section 2.6.3
, Device Documentation:
Updated/Changed the "
Related Documentation From Texas Instruments
" lists
Section 3.2.4
, Tightly Coupled Memory (TCM):
Updated/Changed the "ARM internal ROM ..." sentence
Section 3.5
, Device Clocking,
Section 3.5.1
, Overview:
Updated/Changed "MXI1/MXO
I
"
to
"MXI1/MXO
1
"
Updated/Changted figure reference in "A block diagram of DM355's clocking ..." sentence
Section 3.5.3.1.1
, DM355-270 PLL1 (24 MHz reference):
Table 3-6
, PLL1 Supported Clocking Configurations for DM355-270 (24 MHz reference):
Updated/Changed the VPSS column header
from
"PLLDIV4 (/2 fixed)"
to
"PLLDIV4 (/4 or /2 programmable)"
Section 3.5.3.2.1
, DM355-270 PLL1 (36 MHz reference):
Table 3-8
, PLL1 Supported Clocking Configurations for DM355-270 (36 MHz reference):
Updated/Changed the VPSS column header
from
"PLLDIV4 (/2 fixed)"
to
"PLLDIV4 (/4 or /2 programmable)"
Section 3.11.5.2
, AEMIF Timing Configuration:
Updated/Changed "MXI"
to
"MXI1"
Section 5.3.1
, Power-Supply Sequencing,
Power-On:
and
Power-Off:
:
Deleted the "V
DDA18
" reference for both the
2. Power on 1.8 V
and
2. Power off 1.8 V
rows
Section 5.9.1.1
, CCD Controller (CCDC) Section:
Support for up to
75 MHz
sensor clock (270-MHz speed grade device) bullet:
Updated/Changed speed
from
67.5 MHz
to
75 MHz
Revision History (Revision B)
152
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