參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 131/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
P
5.12
Serial Port Interface (SPI)
5.12.1 SPI Electrical Data/Timing
SPIx_CLK
(Clock Polarity = 0)
1
2
3
SPIx_CLK
(Clock Polarity = 1)
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
The DM355 contains 3 separate SPI modules. These modules provide a programmable length shift
register which allows serial communication with other SPI devices through a 3 or 4 wire interface (Clock,
Data In, Data Out, and Enable). The SPI supports the following features:
Master mode operation
2 chip selects for interfacing to multiple slave SPI devices.
3 or 4 wire interface (Clock, Data In, Data Out, and Enable)
Unique interrupt for each SPI port
Separate DMA events for SPI Receive and Transmit
16-bit shift register
Receive buffer register
Programmable character length (2 to 16 bits)
Programmable SPI clock frequency range
8-bit clock prescaler
Programmable clock phase (delay or no delay)
Programmable clock polarity
The SPI modules do not support the following features:
Slave mode. Only Master mode is supported in DM355 (Master mode means that DM355 provides the
serial clock).
GPIO mode. GPIO functionality is supported by the GIO modules for those SPI pins that are
multiplexed with GPIO signals.
Table 5-28. Timing Requirements for SPI (All Modes)
(1)
(see
Figure 5-36
)
DM355
MIN
NO.
UNIT
MAX
1
2
3
t
c(CLK)
t
w(CLKH)
t
w(CLKL)
Cycle time, SPI_CLK
Pulse duration, SPI_CLK high (All Master Modes)
Pulse duration, SPI_CLK low (All Master Modes
37.037 ns
0.45*T
0.45*T
ns
ns
ns
0.55*T
0.55*T
(1)
T = t
c(CLK)
= SPI_CLK period is equal to the SPI module clock divided by a configurable divider.
Figure 5-36. SPI_CLK Timing
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DM355 Peripheral Information and Electrical Specifications
131
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