參數(shù)資料
型號(hào): TMS320DM355_07
廠商: Texas Instruments, Inc.
英文描述: Digital Media System-on-Chip (DMSoC)
中文描述: 數(shù)字媒體系統(tǒng)芯片(DMSoC)
文件頁數(shù): 60/158頁
文件大?。?/td> 1319K
代理商: TMS320DM355_07
www.ti.com
P
ARM926EJ-S
16K I$
8K D$
MMU
CP15
Arbiter
Arbiter
I-AHB
D-AHB
Master
IF
D
I-TCM
D-TCM
16K
RAM0
RAM1
16K
ROM
8K
Arbiter
Slave
IF
Master IF
C
ARM
Interrupt
Controller
(AINTC)
Control
System
PLLC2
PLLC1
(PSC)
Controller
Sleep
Power
Peripherals
...
3.2 ARM926EJ -S RISC CPU
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Video Processing Back End (VPBE)
On Screen Display (OSD)
Video Encoder Engine (VENC)
Image Pipe (IPIPE)
H3A Engine (Hardware engine for computing Auto-focus, Auto white balance, and Auto exposure)
Figure 3-1
shows the functional block diagram of the DM355 ARM Subsystem.
Figure 3-1. DM355 ARM Subsystem Block Diagram
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
ARM926EJ -S integer core
CP15 system control coprocessor
Memory Management Unit (MMU)
Separate instruction and data Caches
Write buffer
Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces
Separate instruction and data AHB bus interfaces
Detailed Device Description
60
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