參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 107/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
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TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
5.7.1.3
AEMIF Electrical Data/Timing
Table 5-13. Timing Requirements for Asynchronous Memory Cycles for AEMIF Module
(1)
(see
Figure 5-14
and
Figure 5-15
)
DM355
Nom
NO
.
UNIT
MIN
MAX
READS and WRITES
Pulse duration, EM_WAIT assertion and
deassertion
2
t
w(EM_WAIT)
2E
ns
READS
12
13
t
su(EMDV-EMOEH)
t
h(EMOEH-EMDIV)
t
su(EMOEL-
EMWAIT)
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
Delay time from EM_OE low to EM_WAIT
asserted
(2)
5
0
ns
ns
14
4E
ns
READS (OneNAND Synchronous Burst Read)
Setup time, EM_D[15:0] valid before EM_CLK
high
Hold time, EM_D[15:0] valid after EM_CLK high
30
t
su(EMDV-EMCLKH)
4
ns
31
t
h(EMCLKH-EMDIV)
4
ns
WRITES
t
su(EMWEL-
EMWAIT)
Delay time from EM_WE low to EM_WAIT
asserted
(2)
28
4E
ns
(1)
E = PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock. For example,
when PLLC output clock = 432 MHz, E = 9.259 ns. See
Section 3.5
for more information.
Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states.
Figure 5-16
and
Figure 5-17
describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
(2)
Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for AEMIF Module
(1)(2)(3)
(see
Figure 5-14
and
Figure 5-15
)
DM355
UNI
T
NO.
PARAMETER
MIN
Nom
MAX
READS and WRITES
1
t
d(TURNAROUND)
Turn around time
(TA)*E
ns
READS
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E
(RS+RST+RH+(EWC*
ns
3
t
c(EMRCYCLE)
EMIF read cycle time (EW = 1)
ns
16))*E
Output setup time, EM_CE[1:0] low to
EM_OE low (SS = 0)
Output setup time, EM_CE[1:0] low to
EM_OE low (SS = 1)
Output hold time, EM_OE high to
EM_CE[1:0] high (SS = 0)
Output hold time, EM_OE high to
EM_CE[1:0] high (SS = 1)
(RS)*E
ns
4
t
su(EMCEL-EMOEL)
0
ns
(RH)*E
ns
5
t
h(EMOEH-EMCEH)
0
ns
(1)
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256]. See the TMS320DM355 DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (SPRUED1)
for more information.
E = PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock. For example,
when PLLC output clock = 432 MHz, E = 9.259 ns. See
Section 3.5
for more information
EWC = external wait cycles determined by EM_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320DM355 DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (SPRUED1) for more information.
(2)
(3)
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DM355 Peripheral Information and Electrical Specifications
107
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