參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 98/160頁
文件大?。?/td> 559K
代理商: DS2196LN
DS2196
42 of 160
Framer Loopback A
When CCR1A.0 is set to a 1, the A Framer/Formatter will enter a Framer Loopback (FLB) mode. This
loopback is useful in testing and debugging applications. In FLB, the DS2196 will loop data from the
transmit side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all 1’s code will be transmitted at TPOSOA and TNEGOA outputs
2. Data at RPOSIA and RNEGIA will be ignored
3. All receive side signals will take on timing synchronous with TCLKOA instead of RCLKIA.
NOTE:
The signals RCLKA and TCLKA cannot be the same clock during this loopback because this will cause
an unstable condition.
Framer Loopback B
When CCR1B.0 is set to a 1, the B Framer/Formatter will enter a Framer Loopback (FLB) mode. This
loopback is useful in testing and debugging applications. In FLB, the DS2196 will loop data from the
transmit side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all 1’s code will be transmitted at TPOSOB and TNEGOB outputs
2. Data at RPOSIB and RNEGIB will be ignored
3. All receive side signals will take on timing synchronous with TCLKOB instead of RCLKIB.
NOTE:
The signals RCLKB and TCLKB cannot be the same clock during this loopback because this will cause
an unstable condition.
相關(guān)PDF資料
PDF描述
DS21FF44 DATACOM, FRAMER, PBGA300
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DS21FT42 DATACOM, FRAMER, PBGA300
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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