參數(shù)資料
型號： DS2196LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PQFP100
封裝： LQFP-100
文件頁數(shù)： 110/160頁
文件大?。?/td> 559K
代理商： DS2196LN
DS2196
53 of 160
CCR7B: COMMON CONTROL REGISTER 7 FRAMER B (Address = AA Hex)
(MSB)
(LSB)
–
BELB
AIS13-24
AIS1-12
UOP3
UOP2
UOP1
UOP0
SYMBOL
POSITION
NAME AND DESCRIPTION
–
CCR7B.7
Not Assigned. Should be set to 0 when written to.
BELB
CCR7B.6
Back End Loopback.
0 = loopback disabled
1 = loopback enabled
AIS13-24
CCR7B.5
Channels 13 – 24 AIS Enable
0 = do not transmit AIS in channels 13 – 24
1 = transmit AIS in channels 13 - 24
AIS1-12
CCR7B.4
Channels 1 – 12 AIS Enable
0 = do not transmit AIS in channels 1 – 12
1 = transmit AIS in channels 1 - 12
UOP3
CCR7B.3
User Defined Output Pin 3.
0 = logic 0 level at pin
1 = logic 1 level at pin
UOP2
CCR7B.2
User Defined Output Pin 2.
0 = logic 0 level at pin
1 = logic 1 level at pin
UOP1
CCR7B.1
User Defined Output Pin 1.
0 = logic 0 level at pin
1 = logic 1 level at pin
UOP0
CCR7B.0
User Defined Output Pin 0.
0 = logic 0 level at pin
1 = logic 1 level at pin
Remote Loopback
When CCR7A.6 is set to a 1, the 2196 will be forced into Remote Loopback (RLB). In this loopback,
data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins.
Data will continue to pass through the receive side of Framer A as it would normally and the data from
the transmit side of Formatter A will be ignored. Please see Figure 1–1 for more details.
Back End Loopback
When CCR7B.6 is set to a 1, the 2196 will be forced into Back End Loopback (BELB). In this loopback,
data input via the RPOSIB and RNEGIB pins will be transmitted back to the TPOSOB and TNEGOB
pins. Data will continue to pass through the receive side of Framer B as it would normally and the data
from the transmit side of Formatter B will be ignored. Please see Figure 1–1 for more details.
Power–Up Sequence
On power–up, after the supplies are stable, the DS2196 should be configured for operation by writing to
all of the internal registers (this includes setting the Test Registers to 00Hex) since the contents of the
internal registers cannot be predicted on power–up.
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