參數(shù)資料
型號： DS2196LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PQFP100
封裝： LQFP-100
文件頁數(shù)： 37/160頁
文件大?。?/td> 559K
代理商： DS2196LN
DS2196
131 of 160
Table 20-1: Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture
Instruction
Selected Register
Instruction Codes
SAMPLE/PRELOAD
Boundary Scan
010
BYPASS
Bypass
111
EXTEST
Boundary Scan
000
CLAMP
Boundary Scan
011
HIGHZ
Boundary Scan
100
IDCODE
Device Identification
001
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS2196 can be sampled at the boundary scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS2196 to shift data into the boundary scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS2196. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The boundary scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16
bits for the device and 4 bits for the version. See Figure 20-3. Table 20-2 lists the device ID codes for the
DS2196.
Table 20-2: ID CODE STRUCTURE
MSB
LSB
Contents
Version
(Contact Factory)
Device ID
(See Table 20-3)
JEDEC
“00010100001”
“1”
Length
4 bits
16 bits
11 bits
1 bit
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