參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 68/160頁
文件大小: 559K
代理商: DS2196LN
DS2196
16 of 160
Signal Name:
TPOSOA/B / TNRZA/B
Signal Description:
Transmit Positive & NRZ Data Output
Signal Type:
Output
Updated on the rising edge of TCLKOA and rising or falling edge of TCLKOB with either bipolar data or
NRZ data out of the transmit side formatter. This pin can be programmed to source NRZ data via the
Output Data Format (CCR1A.6 and CCR1B.6) control bits.
Signal Name:
TNEGA/B / TFSYNCA/B
Signal Description:
Transmit Negative Data & Frame Sync Pulse Output
Signal Type:
Output
Updated on the rising edge of TCLKA or TCLKB with either bipolar data or a frame sync pulse out of the
transmit side formatter. This pin can be programmed to source the frame sync pulse via the Output Data
Format (CCR1A.6 and CCR1B.6) control bits.
RECEIVE FRAMER PINS
Signal Name:
RCHCLKA/B / RLCLKA/B
Signal Description:
Receive Channel Clock / Receive Link Clock
Signal Type:
Output
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If RCHCLK is
selected, a 192-kHz clock, which pulses high during the LSB of each channel, will be output. If RLCLK
is selected, either a 4 kHz or 2 kHz (ZBTSI) clock for the RLINK data is output. This output signal is
always synchronous with RCLKA or RCLKB.
Signal Name:
RCHBLKA/B / RLINKA/B
Signal Description:
Receive Channel Block / Receive Link Data
Signal Type:
Output
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If RCHBLK is
selected, a user programmable output that can be forced high or low during any of the 24 T1 channels.
Useful for blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels
are used such as Fractional T1, 384 kbps service, 768 kbps, or ISDN–PRI. Also useful for locating
individual channels in drop–and–insert applications, for external per–channel loopback, and for per–
channel conditioning. See Section 21 for details. If RLINK is selected, then either FDL data (ESF) or Fs
bits (D4) or Z bits (ZBTSI) one RCLKA before the start of a frame are output. See Section 21 for details.
This signal is always synchronous with RCLKA or RCLKB.
Signal Name:
RSERA/B
Signal Description:
Receive Serial Data
Signal Type:
Output
Received NRZ serial data. Updated on rising edges of RCLKA or RCLKB.
Signal Name:
RFSYNCA/B
Signal Description:
Receive Frame Sync
Signal Type:
Output
An extracted pulse, one RCLKA or RCLKB wide, is output at this pin which identifies frame boundaries.
Via RCR2A.5 and RCR2B.5, RFSYNC can also be set to output double–wide pulses on signaling frames.
This signal is always synchronous with RCLKA or RCLKB.
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