參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 155/160頁
文件大?。?/td> 559K
代理商: DS2196LN
DS2196
94 of 160
BC2: BERT Control Register 2 (Address = 42 Hex)
(MSB)
(LSB)
EIB2
EIB1
EIB0
SBE
TC
SYMBOL
POSITION
NAME AND DESCRIPTION
EIB2
BC2.7
Error Insert Bit 2. Will automatically insert bit errors at the
prescribed rate into the generated data pattern. Useful for
verifying error detection operation. Refer to Table 15-3 for
details.
EIB1
BC2.6
Error Insert Bit 1. Refer to Table 15-3 for details.
EIB0
BC2.5
Error Insert Bit 0. Refer to Table 15-3 for details.
SBE
BC2.4
Single Bit Error Insert. A low to high transition will create a
single bit error. Must be cleared and set again for a subsequent
bit error to be inserted.
BC2.3
Not Assigned. Should be set to 0 when written.
BC2.2
Not Assigned. Should be set to 0 when written.
BC2.1
Not Assigned. Should be set to 0 when written.
TC
BC2.0
Transmit Pattern Load. A low to high transition loads the
pattern generator with the pattern that is to be generated. This
bit should be toggled from low to high whenever the host
wishes to load a new pattern. Must be cleared and set again for
a subsequent loads.
Table 15-3: BERT RATE INSERTION SELECT
EIB2
EIB1
EIB0
Error Rate Inserted
0
No errors automatically inserted
001
10E-1
010
10E-2
011
10E-3
100
10E-4
101
10E-5
110
10E-6
111
10E-7
相關PDF資料
PDF描述
DS21FF44 DATACOM, FRAMER, PBGA300
DS21FF44N DATACOM, FRAMER, PBGA300
DS21FT40N DATACOM, FRAMER, PBGA300
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
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