參數(shù)資料
型號： DS2196LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PQFP100
封裝： LQFP-100
文件頁數(shù)： 22/160頁
文件大?。?/td> 559K
代理商： DS2196LN
DS2196
118 of 160
TDC2A: TRANSMIT HDLC DS0 CONTROL REGISTER 2 FRAMER A
(Address = 93 Hex)
TDC2B: TRANSMIT HDLC DS0 CONTROL REGISTER 2 FRAMER B
(Address = 97 Hex)
(MSB)
(LSB)
TDB8
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
TDB1
SYMBOL
POSITION
NAME AND DESCRIPTION
TDB8
TDC2.7
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to 1 to stop
this bit from being used.
TDB7
TDC2.6
DS0 Bit 7 Suppress Enable. Set to 1 to stop this bit from
being used.
TDB6
TDC2.5
DS0 Bit 6 Suppress Enable. Set to 1 to stop this bit from
being used.
TDB5
TDC2.4
DS0 Bit 5 Suppress Enable. Set to 1 to stop this bit from
being used.
TDB4
TDC2.3
DS0 Bit 4 Suppress Enable. Set to 1 to stop this bit from
being used.
TDB3
TDC2.2
DS0 Bit 3 Suppress Enable. Set to 1 to stop this bit from
being used.
TDB2
TDC2.1
DS0 Bit 2 Suppress Enable. Set to 1 to stop this bit from
being used.
TDB1
TDC2.0
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to 1 to stop
this bit from being used.
18.2 LEGACY FDL SUPPORT
18.2.1 Overview
The DS2196 maintains the circuitry that existed in the previous generation of Dallas Semiconductor’s
single chip transceivers and quad framers. Section 18.2 covers the circuitry and operation of this legacy
functionality. In new applications, it is recommended that the HDLC controller and BOC controller
described in Section 18.1 be used. On the receive side, it is possible to have both the new HDLC/BOC
controller and the legacy hardware working at the same time. However this is not possible on the transmit
side since there can be only one source the of the FDL data internal to the device.
18.2.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit–by–bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The
framer will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via
IMR2.4, the INT pin will toggle low indicating that the buffer has filled and needs to be read. The user
has 2 ms to read this data before it is lost.
If the byte in the RFDL matches either of the bytes
programmed into the RMTCH1 or RMTCH2 registers, then the SR2.2 bit will be set to a 1 and the INT
pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the
FDL or Fs pattern until an important event occurs.
相關(guān)PDF資料
PDF描述
DS21FF44 DATACOM, FRAMER, PBGA300
DS21FF44N DATACOM, FRAMER, PBGA300
DS21FT40N DATACOM, FRAMER, PBGA300
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2196LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Dual Framer LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS219T 功能描述:烙鐵 DESOLDERING HEAD RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included
DS21E352 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21E352N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21E354 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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