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DS2196
4 of 160
LIST OF FIGURES
Figure 1-1: T1 Dual Framer LIU.............................................................................................................11
Figure 15-1: BERT Mux Diagram...........................................................................................................90
Figure 19-1: External Analog Connections...........................................................................................124
Figure 19-2: Jitter Tolerance .................................................................................................................125
Figure 19-3: Transmit Waveform Template ........................................................................................125
Figure 19-4: Jitter Attenuation ..............................................................................................................126
Figure 20-1: Boundary Scan Architecture............................................................................................127
Figure 20-2: TAP Controller State Machine ........................................................................................130
Figure 21-1: Receive Side D4 Timing ....................................................................................................136
Figure 21-2: Receive Side ESF Timing..................................................................................................137
Figure 21-3: Receive Side Boundary Timing........................................................................................138
Figure 21-4: Transmit Side D4 Timing .................................................................................................139
Figure 21-5: Transmit Side ESF Timing...............................................................................................140
Figure 21-6: Transmit Side Boundary Timing.....................................................................................141
Figure 21-7: Transmit Data Flow ..........................................................................................................142
Figure 21-8: Receive Data Flow .............................................................................................................143
Figure 22-1: Intel Bus Read AC Timing (BTS=0 / MUX = 1).............................................................149
Figure 22-2: Intel Bus Write Timing (BTS=0 / MUX=1) ....................................................................150
Figure 22-3: Motorola Bus AC Timing (BTS = 1 / MUX = 1).............................................................151
Figure 22-4: Intel Bus Read AC Timing (BTS=0 / MUX=0)...............................................................152
Figure 22-5: Intel Bus Write AC Timing (BTS=0 / MUX=0)..............................................................153
Figure 22-6: Motorola Bus Read AC Timing (BTS=1 / MUX=0).......................................................154
Figure 22-7: Motorola Bus Write AC Timing (BTS=1 / MUX=0)......................................................155
Figure 22-8: Receive Side AC Timing ...................................................................................................156
Figure 22-9: Receive Line Interface AC Timing ..................................................................................157
Figure 22-10: Transmit Side AC Timing ..............................................................................................158
Figure 22-11: Transmit Line Interface Side AC Timing .....................................................................159