參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 107/160頁
文件大?。?/td> 559K
代理商: DS2196LN
DS2196
50 of 160
CCR5B: COMMON CONTROL REGISTER 5 FRAMER B (Address = B9 Hex)
(MSB)
(LSB)
TJC
TCM4
TCM3
TCM2
TCM1
TCM0
SYMBOL
POSITION
NAME AND DESCRIPTION
TJC
CCR5B.7
Transmit Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
CCR5B.6
Not Assigned. Must be set to 0 when written.
CCR5B.5
Not Assigned. Must be set to 0 when written.
TCM4
CCR5B.4
Transmit Channel Monitor Bit 4. MSB of a channel decode
that determines which transmit channel data will appear in the
TDS0M register. See Section 10 for details.
TCM3
CCR5B.3
Transmit Channel Monitor Bit 3.
TCM2
CCR5B.2
Transmit Channel Monitor Bit 2.
TCM1
CCR5B.1
Transmit Channel Monitor Bit 1.
TCM0
CCR5B.0
Transmit Channel Monitor Bit 0. LSB of the channel decode.
CCR6A: COMMON CONTROL REGISTER 6 FRAMER A (Address = 1E Hex)
(MSB)
(LSB)
RJC
EAMS
MECU
RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION
NAME AND DESCRIPTION
RJC
CCR6A.7
Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
EAMS
CCR6A.6
Error Accumulation Mode Select.
0 = CCR3A.2 determines accumulation time
1 = CCR6A.5 determines accumulation time
MECU
CCR6A.5
Manual Error Counter Update. When enabled by CCR6A.6,
the changing of this bit from a 0 to a 1 allows the next clock
cycle to load the error counter registers with the latest counts
and reset the counters. The user must wait a minimum of 972
ns (1.5 clock periods) before reading the error count registers to
allow for proper update.
RCM4
CCR6A.4
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 10 for details.
RCM3
CCR6A.3
Receive Channel Monitor Bit 3.
RCM2
CCR6A.2
Receive Channel Monitor Bit 2.
RCM1
CCR6A.1
Receive Channel Monitor Bit 1.
RCM0
CCR6A.0
Receive Channel Monitor Bit 0. LSB of the channel decode.
CCR6B: COMMON CONTROL REGISTER 6 FRAMER B (Address = BE Hex)
相關(guān)PDF資料
PDF描述
DS21FF44 DATACOM, FRAMER, PBGA300
DS21FF44N DATACOM, FRAMER, PBGA300
DS21FT40N DATACOM, FRAMER, PBGA300
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
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