參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 101/160頁
文件大小: 559K
代理商: DS2196LN
DS2196
45 of 160
CCR3A: COMMON CONTROL REGISTER 3 FRAMER A (Address = 30 Hex)
(MSB)
(LSB)
LIDST
TCLKSRC
RLOS
RSMS
FBCT2
ECUS
TLOOP
FBCT1
SYMBOL
POSITION
NAME AND DESCRIPTION
LIDST
CCR3A.7
Line Interface TX Digital Signal Tri-state. Tri-state control
for the LIU pins LFSYNC, LCLK and LNRZ.
0 = pins not tri-stated
1 = pins tri-stated
TCLKSRC
CCR3A.6
Transmit Clock Source Select. This function allows the user
to internally select MCLK as the clock source for the transmit
side formatter.
0 = TCLK supplied by LOTC mux (see TCR1A.7)
1 = use MCLK for TCLK
RLOSF
CCR3A.5
Function of the RLOSA/LOTCA Output.
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
RSMS
CCR3A.4
RMSYNCA Multiframe Skip Control. Useful in framing
format conversions from D4 to ESF.
0 = RMSYNCA will output a pulse at every multiframe
1 = RMSYNCA will output a pulse at every other multiframe
FBCT2
CCR3A.3
F Bit Corruption Type 2. Setting this bit high enables the
corruption of one Ft (D4 framing mode) or FPS (ESF framing
mode) bit in every 128 Ft or FPS bits as long as the bit remains
set.
ECUS
CCR3A.2
Error Counter Update Select. Selects the update rate of the
error counters and the period of the One Second Timer
(SR2A.5). See Sections 7 & 8 for details.
0 = update error counters once a second
1 = update error counters every 42 ms (333 frames)
TLOOP
CCR3A.1
Transmit Loop Code Enable. See Section 12 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as
defined in TCD register
FBCT1
CCR3A.0
F Bit Corruption Type 1. A low to high transition of this bit
causes the next three consecutive Ft (D4 framing mode) or FPS
(ESF framing mode) bits to be corrupted causing the remote end
to experience a loss of synchronization.
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