the I
參數(shù)資料
型號(hào)： ADUC7126BSTZ126-RL
廠商： Analog Devices Inc
文件頁數(shù)： 78/108頁
文件大?。?/td> 0K
描述： IC MCU 16/32B 126KB FLASH 80LQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 帶卷 (TR)
Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 71 of 108
Master Mode
In master mode, the I2CxADR0 register is programmed with
the I2C address of the device.
In 7-bit address mode, I2CxADR0[7:1] are set to the device
address. I2CxADR0[0] is the read/write bit.
In 10-bit address mode, the 10-bit address is created as follows:
I2CxADR0[7:3] must be set to 11110b.
I2CxADR0[2:1] = Address Bits[9:8].
I2CxADR1[7:0] = Address Bits[7:0].
I2CxADR0[0] is the read/write bit.
I2C Registers
The I2C peripheral interfaces consists of a number of MMRs.
These are described in the I2C Master Registers section.
I2C Master Registers
I2C Master Control Register
Name:
I2C0MCON, I2C1MCON
Address:
0xFFFF0800, 0xFFFF0900
Default
Value:
0x0000, 0x0000
Access:
Read/write
Function:
This 16-bit MMR configures the I2C peripheral in
master mode.
Table 102. I2CxMCON MMR Bit Descriptions
Bit
Name
Description
[15:9]
Reserved. These bits are reserved and should not be written to.
8
I2CMCENI
I2C transmission complete interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I2C bus.
Clear this bit to clear the interrupt source.
7
I2CNACKENI
I2C no acknowledge (NACK) received interrupt enable bit.
Set this bit to enable interrupts when the I2C master receives a NACK.
Clear this bit to clear the interrupt source.
6
I2CALENI
I2C arbitration lost interrupt enable bit.
Set this bit to enable interrupts when the I2C master is unable to gain control of the I2C bus.
Clear this bit to clear the interrupt source.
5
I2CMTENI
I2C transmit interrupt enable bit.
Set this bit to enable interrupts when the I2C master has transmitted a byte.
Clear this bit to clear the interrupt source.
4
I2CMRENI
I2C receive interrupt enable bit.
Set this bit to enable interrupts when the I2C master receives data.
Cleared by user to disable interrupts when the I2C master is receiving data.
I2CMSEN
I2C master SCL stretch enable bit.
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
3
Clear this bit to disable clock stretching.
2
I2CILEN
I2C internal loopback enable.
Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their
respective input signals.
Cleared by the user to disable loopback mode.
1
I2CBD
I2C master backoff disable bit.
Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start
condition.
Clear this bit to wait until the I2C bus becomes free.
0
I2CMEN
I2C master enable bit.
Set by the user to enable I2C master mode.
Clear this bit to disable I2C master mode.
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