參數(shù)資料
型號： ADUC7126BSTZ126-RL
廠商： Analog Devices Inc
文件頁數(shù)： 56/108頁
文件大?。?/td> 0K
描述： IC MCU 16/32B 126KB FLASH 80LQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 帶卷 (TR)
Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 51 of 108
OTHER ANALOG PERIPHERALS
DAC
The ADuC7124/ADuC7126 incorporate two, or four, 12-bit
voltage output DACs on chip, depending on the model. Each
DAC has a rail-to-rail voltage output buffer capable of driving
5 kΩ/100 pF.
Each DAC has three selectable ranges: 0 V to VREF (internal
band gap 2.5 V reference), 0 V to DACREF, and 0 V to AVDD.
DACREF is equivalent to an external reference for the DAC.
The signal range is 0 V to AVDD.
MMRs Interface
Each DAC is independently configurable through a control
register and a data register. These two registers are identical for
the four DACs. Only DAC0CON (see Table 63) and DAC0DAT
(see Table 65) are described in detail in this section.
Table 62. DACxCON Registers
Name
Address
Default Value
Access
DAC0CON
0xFFFF0600
0x00
R/W
DAC1CON
0xFFFF0608
0x00
R/W
DAC2CON
0xFFFF0610
0x00
R/W
DAC3CON
0xFFFF0618
0x00
R/W
Table 63. DAC0CON MMR Bit Descriptions
Bit
Value
Name
Description
[7:6]
Reserved.
5
DACCLK
DAC update rate.
Set by the user to update the DAC
using Timer1.
Cleared by the user to update the
DAC using HCLK (core clock).
4
DACCLR
DAC clear bit.
Set by the user to enable normal
DAC operation.
Cleared by the user to reset the data
register of the DAC to 0.
3
Reserved. This bit should be left at 0.
2
Reserved. This bit should be left at 0.
[1:0]
DAC range bits.
00
Power-down mode. The DAC output
is in tristate.
01
0 V to DACREF range.
10
0 V to VREF (2.5 V) range.
11
0 V to AVDD range.
Table 64. DACxDAT Registers
Name
Address
Default Value
Access
DAC0DAT
0xFFFF0604
0x00000000
R/W
DAC1DAT
0xFFFF060C
0x00000000
R/W
DAC2DAT
0xFFFF0614
0x00000000
R/W
DAC3DAT
0xFFFF061C
0x00000000
R/W
Table 65. DAC0DAT MMR Bit Descriptions
Bit
Description
[31:28]
Reserved.
[27:16]
12-bit data for DAC0.
[15:0]
Reserved.
Using the DACs
The on-chip DAC architecture consists of a DAC resistor string
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 41.
09
12
3-
02
3
R
DAC0
VREF
AVDD
DACREF
Figure 41. DAC Structure
As illustrated in Figure 41, the reference source for each DAC is
user selectable in software. It can be either AVDD, VREF, or DACREF.
In 0 V-to-AVDD mode, the DAC output transfer function spans
from 0 V to the voltage at the AVDD pin. In 0 V-to-DACREF mode,
the DAC output transfer function spans from 0 V to the voltage at
the DACREF pin. In 0 V-to-VREF mode, the DAC output transfer
function spans from 0 V to the internal 2.5 V reference, VREF.
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that, when unloaded,
each output is capable of swinging to within less than 5 mV of
both AVDD and ground. Moreover, the DAC linearity specification
(when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function except the 0 to 100 codes,
and, in 0 V-to-AVDD mode only, Code 3995 to Code 4095.
Linearity degradation near ground and VDD is caused by satu-
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is illustrated in Figure 42.
The dotted line in Figure 42 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 42 represents a transfer function
in 0 V-to-AVDD mode only. In 0 V-to-VREF or 0 V-to-DACREF
mode (with VREF < AVDD or DACREF < AVDD), the lower nonlinear-
ity is similar. However, the upper portion of the transfer function
follows the ideal line right to the end (VREF in this case, not AVDD),
showing no signs of endpoint linearity errors.
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