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參數(shù)資料
| 型號： | ADUC7126BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16/32B 126KB FLASH 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 40 |
| 程序存儲(chǔ)器容量： | 126KB（63K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x12b，D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 帶卷 (TR) |
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ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 102 of 108
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of the
ADuC7124/ADuC7126-based designs to achieve optimum
performance from the ADCs and DAC.
Although the part has separate pins for analog and digital ground
(AGND and IOGND), the user must not tie these to two sepa-
rate ground planes unless the two ground planes are connected
very close to the part. This is illustrated in the simplified example
shown in Figure 66a. In systems where digital and analog
ground planes are connected together somewhere else (at the
power supply of the system, for example), the planes cannot be
reconnected near the part because a ground loop results. In these
cases, tie all the ADuC7124/ADuC7126 AGND and IOGND
pins to the analog ground plane, as illustrated in Figure 66b.
In systems with only one ground plane, ensure that the digital
and analog components are physically separated onto separate
halves of the board so that digital return currents do not flow
near analog circuitry (and vice versa).
The ADuC7124/ADuC7126 can then be placed between the
digital and analog sections, as illustrated in Figure 66c.
09
12
3-
0
47
a.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
b.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
c.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
DGND
Figure 66. System Grounding Schemes
In all of these scenarios, and in more complicated real-life
applications, the users should pay particular attention to the
flow of current from the supplies and back to ground. Make
sure the return paths for all currents are as close as possible to
the paths the currents took to reach their destinations.
For example, do not power components on the analog side (as
currents from IOVDD to flow through AGND. Avoid digital
currents flowing under analog circuitry, which can occur if a
noisy digital chip is placed on the left half of the board (shown
in Figure 66c). If possible, avoid large discontinuities in the
ground plane(s), such as those formed by a long trace on the same
layer, because they force return signals to travel a longer path.
In addition, make all connections to the ground plane directly,
with little or no trace separating the pin from its via to ground.
When connecting fast logic signals (rise/fall time < 5 ns) to any of
the ADuC7124/ADuC7126 digital inputs, add a series resistor to
each relevant line to keep rise and fall times longer than 5 ns at
the input pins of the part. A value of 100 Ω or 200 Ω is usually
sufficient to prevent high speed signals from coupling capaci-
tively into the part and affecting the accuracy of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7124/ADuC7126 can be generated
by the internal PLL or by an external clock input. To use the
internal PLL, connect a 32.768 kHz parallel resonant crystal
between XCLKI and XCLKO, and connect a capacitor from
each pin to ground as shown in Figure 67. The crystal allows the
PLL to lock correctly to give a frequency of 41.78 MHz. If no
external crystal is present, the internal oscillator is used to give
a typical frequency of 32.768 kHz ± 3%.
09123
-048
ADuC7124/
ADuC7126
TO
INTERNAL
PLL
12pF
XCLKI
32.768kHz
12pF
XCLKO
Figure 67. External Parallel Resonant Crystal Connections
To use an external source clock input instead of the PLL (see
Figure 68), Bit 1 and Bit 0 of PLLCON must be modified. The
external clock uses P0.7 and XCLK.
09123
-049
ADuC7124/
ADuC7126
TO
FREQUENCY
DIVIDER
XCLKO
XCLKI
XCLK
EXTERNAL
CLOCK
SOURCE
Figure 68. Connecting an External Clock Source
Using an external clock source, the ADuC7124/ADuC7126
specified operational clock speed range is 50 kHz to 41.78 MHz
± 1%, which ensures correct operation of the analog peripherals
and Flash/EE.
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