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參數(shù)資料
| 型號： | ADUC7126BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16/32B 126KB FLASH 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 40 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x12b，D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 帶卷 (TR) |
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ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 42 of 108
CALIBRATION
By default, the factory-set values written to the ADC offset
(ADCOF) and gain coefficient registers (ADCGN) yield opti-
mum performance in terms of end-point errors and linearity
for standalone operation of the part (see the Specifications
section). If system calibration is required, it is possible to
modify the default offset and gain coefficients to improve end-
point errors, but note that any modification to the factory-set
ADCOF and ADCGN values can degrade ADC linearity
performance.
For system offset error correction, the ADC channel input stage
must be tied to AGND. A continuous software ADC conversion
loop must be implemented by modifying the value in ADCOF
until the ADC result (ADCDAT) reads Code 0 to Code 1. If the
ADCDAT value is greater than 1, ADCOF should be decremented
until ADCDAT reads Code 0 to Code 1. Offset error correction
is done digitally and has a resolution of 0.25 LSB and a range of
±3.125% of VREF.
For system gain error correction, the ADC channel input stage
must be tied to VREF. A continuous software ADC conversion
loop must be implemented to modify the value in ADCGN until
the ADC result (ADCDAT) reads Code 4094 to Code 4095. If the
ADCDAT value is less than 4094, ADCGN should be incremented
until ADCDAT reads Code 4094 to Code 4095. Similar to the
offset calibration, the gain calibration resolution is 0.25 LSB
with a range of ±3% of VREF.
TEMPERATURE SENSOR
The ADuC7124/ADuC7126 provide voltage outputs from an
on-chip band gap reference that is proportional to absolute
temperature. This voltage output can also be routed through the
front-end ADC multiplexer (effectively, an additional ADC
channel input), facilitating an internal temperature sensor
channel, measuring die temperature.
An ADC temperature sensor conversion differs from a standard
ADC voltage. The ADC performance specifications do not
apply to the temperature sensor.
Chopping of the internal amplifier must be enabled using the
TSCON register. To enable this mode, the user must set Bit 0 of
TSCON. The user must also take two consecutive ADC readings
and average them in this mode.
The ADCCON register must be configured to 0x37A3.
To calculate die temperature, use the following formula:
T – TREF = (VADC – VTREF) × K
where:
T is the temperature result.
TREF = 25°C.
For the ADuC7124, VTREF = 1.415 V and for the ADuC7126,
VTREF = 1.392 V, which corresponds to TREF = 25°C, as described
in Table 1.
VADC is the average ADC result from two consecutive
conversions.
K is the gain of the ADC in temperature sensor mode as
determined by characterization data. K = 0.2555°C/mV
for ADuC7124. K = 0.2212°C/mV for ADuC7126. This
corresponds to the 1/voltage temperature coefficient
specification from Table 1.
Using the default values from Table 1 and without any
calibration, this equation becomes
T 25°C = (VADC 1415) × 0.2555 for ADuC7124
T 25°C = (VADC 1392) × 0.2212 for ADuC7126
where VADC is in mV.
For better accuracy, the user should perform a single point
calibration at a controlled temperature value.
For the calculation with no calibration, use 25°C and 1415 mV
for the ADuC7124 and 1392mV for the ADuC7126. The idea
of a single point calibration is to use other known (TREF, VTREF)
values to replace the common T = 25°C and 1415 mV for the
ADuC7124 and 1392 mV for the ADuC7126 for every part.
For some users, it is not possible to obtain such a known pair.
For such cases, the ADuC7124/ADuC7126 comes with a single
point calibration value loaded in the TEMPREF register. For
more details on this register, see Table 35. During production
testing of the ADuC7124/ADuC7126, the TEMPREF register is
loaded with an offset adjustment factor. Each part has a
different value in the TEMPREF register. Using this single point
calibration, the same formula is still used.
T – TREF = (VADC – VTREF) × K
where:
TREF = 25°C but is not guaranteed.
VTREF can be calculated using the TEMPREF register.
TSCON Register
Name:
TSCON
Address:
0xFFFF0544
Default Value:
0x00
Access:
Read/write
Table 34. TSCON MMR Bit Descriptions
Bit
Description
[7:1]
Reserved.
0
Temperature sensor chop enable bit. This bit must
be set.
This bit is set to 1 to enable chopping of the internal
amplifier to the ADC.
This bit is cleared to disable chopping. This results in
incorrect temperature sensor readings.
This bit is cleared by default.
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