參數(shù)資料
型號： ADUC7126BSTZ126-RL
廠商： Analog Devices Inc
文件頁數(shù)： 45/108頁
文件大小： 0K
描述： IC MCU 16/32B 126KB FLASH 80LQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 帶卷 (TR)
Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 41 of 108
Single-Ended Mode
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-
pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This can necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application. Figure 37 and Figure 38 give an
example of the ADC front end.
In single-ended mode, SW2 is always connected internally to
ground. The VIN pin can be floating. The input signal range on
VIN+ is 0 V to VREF.
0912
3
-0
2
0
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
CS
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
091
23-
0
61
ADuC7124/
ADuC7126
ADC0
10
0.01F
Figure 35. ADC in Single-Ended Mode
Analog Input Structure
Figure 37. Buffering Single-Ended/Pseudo Differential Input
Figure 36 shows the equivalent circuit of the analog input structure
of the ADC. The four diodes provide ESD protection for the analog
inputs. Care must be taken to ensure that the analog input
signals never exceed the supply rails by more than 300 mV; this
can cause these diodes to become forward-biased and start
conducting into the substrate. These diodes can conduct up to
10 mA without causing irreversible damage to the part.
09
12
3-
0
62
ADuC7124/
ADuC7126
ADC0
VREF
ADC1
Figure 38. Buffering Differential Inputs
The C1 capacitors in Figure 36 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the sampling capacitors of the ADC and
typically have a capacitance of 16 pF.
When no amplifier is used to drive the analog input, the source
impedance should be limited to values lower than 1 kΩ. The
maximum source impedance depends on the amount of total
harmonic distortion (THD) that can be tolerated. The THD
increases as the source impedance increases and the performance
degrades.
AVDD
C1
D
R1 C2
AVDD
C1
D
R1 C2
09
12
3
-0
21
DRIVING THE ANALOG INPUTS
Internal or external references can be used for the ADC. In
differential mode of operation, there are restrictions on the
common-mode input signal (VCM), which is dependent upon
the reference value and supply voltage used to ensure that the
signal remains within the supply rails. Table 33 gives some
calculated VCM minimum and VCM maximum values.
Figure 36. Equivalent Analog Input Circuit Conversion Phase: Switches Open,
Track Phase: Switches Closed
Table 33. VCM Ranges
AVDD
VREF
VCM Minimum
VCM Maximum
Signal Peak-to-Peak
2.5 V
1.25 V
2.05 V
2.5 V
2.048 V
1.024 V
2.276 V
3.3 V
1.25 V
0.75 V
2.55 V
2.048 V
1.25 V
2.5 V
1.25 V
1.75 V
2.5 V
2.048 V
1.024 V
1.976 V
3.0 V
1.25 V
0.75 V
2.25 V
2.048 V
1.25 V
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