AVDD AV
參數(shù)資料
型號(hào)： ADUC7126BSTZ126-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 57/108頁(yè)
文件大?。?/td> 0K
描述： IC MCU 16/32B 126KB FLASH 80LQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 帶卷 (TR)
ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 52 of 108
09
12
3-
0
24
AVDD
AVDD – 100mV
100mV
0x00000000
0x0FFF0000
Figure 42. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in Figure 42
becomes worse as a function of output loading. Most of the
ADuC7124/ADuC7126 data sheet specifications assume a 5 kΩ
resistive load to ground at the DAC output. As the output is
forced to source or sink more current, the nonlinear regions at
the top or bottom (respectively) of Figure 42 become larger.
With larger current demands, this can significantly limit output
voltage swing.
References to ADC and the DACs
The ADC and DACs can be configured to use the internal VREF
or an external reference as a reference source. The internal VREF
must work with an external 0.47 μF capacitor.
Table 66. Reference Source Selection for the ADC and DACs
REFCON[0]
DACxCON[1:0]
Description
0
00
ADC works with an external
reference. DACs are powered
down.
0
01
ADC works with an external
reference. DAC works with
DACREF.
0
10
Reserved.
0
11
ADC works with an external
reference. DACs work with
internal AVDD.
1
00
ADC works with an internal VREF.
DACs are powered down.
1
01
ADC works with an external
reference. DACs work with
DACREF.
1
10
ADC and DACs work with an
internal VREF.
1
11
ADC works with an internal VREF.
DACs work with an internal
AVDD.
Note that if REFCON[1] = 1, the internal VREF powers down
and the ADC cannot use the internal VREF.
Configuring DAC Buffers in Op Amp Mode
In op amp mode, the DAC output buffers are used as an op amp
with the DAC itself disabled.
If DACBCFG Bit 0 is set, ADC0 is the positive input to the op
amp, ADC1 is the negative input, and DAC0 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC0CON.
If DACBCFG Bit 1 is set, ADC2 is the positive input to the op
amp, ADC3 is the negative input, and DAC1 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC1CON.
If DACBCFG Bit 2 is set, ADC4 is the positive input to the op
amp, ADC5 is the negative input, and DAC2 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC2CON.
If DACBCFG Bit 3 is set, ADC8 is the positive input to the op
amp, ADC9 is the negative input, and DAC3 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC3CON.
DACBCFG Register
Name:
DACBCFG
Address:
0xFFFF0654
Default Value:
0x00
Access:
Read/write
Table 67. DACBCFG MMR Bit Descriptions
Bit
Description
[7:4]
Reserved. Always set to 0.
3
Set this bit to 1 to configure the DAC3 output
buffer in op amp mode.
Clear this bit for the DAC buffer to operate as
normal.
2
Set this bit to 1 to configure the DAC2 output
buffer in op amp mode.
Clear this bit for the DAC buffer to operate as
normal.
1
Set this bit to 1 to configure the DAC1 output
buffer in op amp mode.
Clear this bit for the DAC buffer to operate as
normal.
0
Set this bit to 1 to configure the DAC0 output
buffer in op amp mode.
Clear this bit for the DAC buffer to operate as
normal.
The DACBCFG write sequence is as follows:
1.
Write Code 0x9A to Register DACBKEY1.
2.
Write user value to Register DACBCFG.
3.
Write Code 0x0C to Register DACBKEY2.
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