參數(shù)資料
型號： ADUC7126BSTZ126-RL
廠商： Analog Devices Inc
文件頁數(shù)： 31/108頁
文件大小： 0K
描述： IC MCU 16/32B 126KB FLASH 80LQFP
標準包裝： 1,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 帶卷 (TR)
Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 29 of 108
MEMORY ORGANIZATION
The ADuC7124/ADuC7126 incorporate three separate blocks
of memory: 32 kB of SRAM and two 64 kB blocks of on-chip
Flash/EE memory. There are 126 kB of on-chip Flash/EE memory
available to the user, and the remaining 2 kB are reserved for the
system kernel. These blocks are mapped as shown in Figure 24.
Note that, by default, after a reset, the Flash/EE memory is
mirrored at Address 0x00000000. It is possible to remap the
SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP
MMR. This remap function is described in more detail in the
Flash/EE memory chapter.
RESERVED
0x00080000
FLASH/EE
RESERVED
0x00047FFF
0x00040000
SRAM
0xFFFF0000
0xFFFFFFFF
MMRs
0x0001FFFF
0x00000000
0x0009F800
RESERVED
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
09
12
3-
02
5
Figure 24. Physical Memory Map
MEMORY ACCESS
The ARM7 core sees memory as a linear array of a 232 byte
location where the different blocks of memory are mapped as
outlined in Figure 24.
The ADuC7124/ADuC7126 memory organization is configured
in little endian format: the least significant byte is located in the
lowest byte address and the most significant byte in the highest
byte address.
BIT 31
BYTE 2
A
6
2
.
BYTE 3
B
7
3
.
BYTE 1
9
5
1
.
BYTE 0
8
4
0
.
BIT 0
32 BITS
0xFFFFFFFF
0x00000004
0x00000000
09
12
3-
02
6
Figure 25. Little Endian Format
FLASH/EE MEMORY
The 128 kB of Flash/EE are organized as two banks of 32 kB ×
16 bits. In the first block, 31 kB × 16 bits is user space and 1 kB
× 16 bits is reserved for the factory-configured boot page. The
page size of this Flash/EE memory is 512 bytes.
The second 64 kB block is organized in a similar manner. It is
arranged in 32 kB × 16 bits. All of this is available as user space.
The 126 kB of Flash/EE are available to the user as code and
nonvolatile data memory. There is no distinction between data
and program because ARM code shares the same space. The
real width of the Flash/EE memory is 16 bits, meaning that, in
ARM mode (32-bit instruction), two accesses to the Flash/EE
are necessary for each instruction fetch. Therefore, it is recom-
mended that Thumb mode be used when executing from
Flash/EE memory for optimum access speed. The maximum
access speed for the Flash/EE memory is 41.78 MHz in Thumb
mode and 20.89 MHz in full ARM mode (see the Execution
SRAM
The 32 kB of SRAM are available to the user, organized as
8 kB × 32 bits, that is, 16 kB words. ARM code can run directly
from SRAM at 41.78 MHz, given that the SRAM array is
configured as a 32-bit wide memory array (see the Execution
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and accessed by indirect
addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and
all on-chip peripherals. All registers except the core registers
reside in the MMR area. All shaded locations shown in Figure 26
are unoccupied or reserved locations and should not be
accessed by user software. Table 11 to Table 29 show the full
MMR memory map.
The access time reading or writing a MMR depends on the
advanced microcontroller bus architecture (AMBA) bus used
to access the peripheral. The processor has two AMBA buses:
the advanced high performance bus (AHB) used for system
modules, and the advanced peripheral bus (APB) used for the
lower performance peripheral. Access to the AHB is one cycle,
and access to the APB is two cycles. All peripherals on the
ADuC7124/ADuC7126 are on the APB except the Flash/EE
memory and the GPIOs.
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