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參數(shù)資料
| 型號： | ADUC7126BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 41/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16/32B 126KB FLASH 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 40 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x12b，D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 帶卷 (TR) |
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ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 38 of 108
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
The top four bits are the sign bits. The 12-bit result is placed in
Bit 16 to Bit 27 as shown in Figure 30. Again, it should be noted
that in fully differential mode, the result is represented in twos
complement format. In pseudo differential and single-ended
modes, the result is represented in straight binary format.
09
12
3-
01
4
SIGN BITS
12-BIT ADC RESULT
31
27
16 15
0
Figure 30. ADC Result Format
The same format is used in DACxDAT, simplifying the software.
Current Consumption
The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 μA. The internal reference
adds 140 μA. During conversion, the extra current is 0.3 μA
multiplied by the sampling frequency (in kHz).
Timing
Figure 31 gives details of the ADC timing. The user controls the
ADC clock speed and the number of acquisition clocks in the
ADCCON MMR. By default, the acquisition time is eight
clocks, and the clock divider is two. The number of extra clocks
(such as bit trial or write) is set to 19, which gives a sampling
rate of 774 kSPS. For conversion on temperature sensor, the
ADC acquisition time is automatically set to 16 clocks, and the
ADC clock divider is set to 32. When using multiple channels
including the temperature sensor, the timing settings revert to
the user-defined settings after reading the temperature sensor
channel.
0
912
3-
015
ADC CLOCK
ACQ
BIT TRIAL
DATA
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
WRITE
CONVSTART
ADCBUSY
ADCDAT
Figure 31. ADC Timing
MMRS INTERFACE
The ADC is controlled and configured via the eight MMRs.
ADCCON Register
Name:
ADCCON
Address:
0xFFFF0500
Default Value:
0x0600
Access:
Read/write
ADCCON is an ADC control register that allows the program-
mer to enable the ADC peripheral, select the mode of operation
of the ADC (either in single-ended mode, pseudo differential
mode, or fully differential mode), and select the conversion
type. This MMR is described in Table 30.
Table 30. ADCCON MMR Bit Descriptions
Bit
Value
Description
[15:14]
Reserved.
13
Set by the user to enable edge trigger mode.
Cleared by the user to enable level trigger
mode.
[12:10]
ADC clock speed.
000
fADC/1. This divider is provided to obtain
1 MSPS ADC with an external clock <41.78 MHz.
001
fADC/2 (default value).
010
fADC/4.
011
fADC/8.
100
fADC/16.
101
fADC/32.
[9:8]
ADC acquisition time.
00
Two clocks.
01
Four clocks.
10
Eight clocks (default value).
11
16 clocks.
7
Enable start conversion.
Set by the user to start any type of
conversion command.
Cleared by the user to disable a start
conversion (clearing this bit does not stop
the ADC when continuously converting).
6
Enable ADCBUSY.
Set by the user to enable the ADCBUSY pin.
Cleared by the user to disable the ADCBUSY pin.
5
ADC power control.
Set by the user to place the ADC in normal
mode (the ADC must be powered up for at least
5 μs before it converts correctly).
Cleared by the user to place the ADC in power-
down mode.
[4:3]
Conversion mode.
00
Single-ended mode.
01
Differential mode.
10
Pseudo differential mode.
11
Reserved.
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