參數(shù)資料
型號(hào)： ADUC7126BSTZ126-RL
廠商： Analog Devices Inc
文件頁數(shù)： 106/108頁
文件大小： 0K
描述： IC MCU 16/32B 126KB FLASH 80LQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 帶卷 (TR)
Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 97 of 108
T3CLRI Register
Name:
T3CLRI
Address:
0xFFFF036C
Default Value:
0x00
Access:
Write only
T3CLRI is an 8-bit register. Writing any value to this register on
successive occassions clears the Timer3 interrupt in normal
mode or resets a new timeout period in watchdog mode.
Note that the user must perform successive writes to this
register to ensure resetting the timeout period.
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to T3CLRI
to avoid a watchdog reset. The value is a sequence generated
by the 8-bit linear feedback shift register (LFSR) polynomial =
X8 + X6 + X5 + X + 1, as shown in Figure 56.
0
9123-
03
8
CLOCK
QD
4
QD
5
QD
3
QD
7
QD
6
QD
2
QD
1
QD
0
Figure 56. 8-Bit LFSR
The initial value or seed is written to T3CLRI before entering
watchdog mode. After entering watchdog mode, a write to
T3CLRI must match this expected value. If it matches, the LFSR
is advanced to the next state when the counter reload occurs. If
it fails to match the expected state, a reset is immediately
generated, even if the count has not yet expired.
The value 0x00 should not be used as an initial seed due to the
properties of the polynomial. The value 0x00 is always guaran-
teed to force an immediate reset. The value of the LFSR cannot
be read; it must be tracked/generated in software.
Example of a sequence:
1.
Enter initial seed, 0xAA, in T3CLRI before starting Timer3
in watchdog mode.
2.
Enter 0xAA in T3CLRI; Timer3 is reloaded.
3.
Enter 0x37 in T3CLRI; Timer3 is reloaded.
4.
Enter 0x6E in T3CLRI; Timer3 is reloaded.
5.
Enter 0x66. 0xDC was expected; the watchdog resets the chip.
EXTERNAL MEMORY INTERFACING
The ADuC7124/ADuC7126 feature an external memory
interface. The external memory interface requires a larger
number of pins. The XMCFG MMR must be set to 1 to use the
external port.
Although 32-bit addresses are supported internally, only the
lower 16 bits of the address are on external pins.
The memory interface can address up to four 128 kB of
asynchronous memory (SRAM or/and EEPROM).
The pins required for interfacing to an external memory are
shown in Table 146.
Table 146. External Memory Interfacing Pins
Pin
Function
AD[15:0]
Address/data bus.
A16
Extended addressing for 8-Bit memory only.
MS[3:0]
Memory select.
WS
Write strobe.
RS
Read strobe.
AE
Address latch enable.
BHE, BLE
Byte write capability.
There are four external memory regions available as described
in Table 147. Associated with each region are the MS[3:0] pins.
These signals allow access to the particular region of external
memory. The size of each memory region can be 128 kB maxi-
mum, 64 k × 16 or 128 kB × 8. To access 128 kB with an 8-bit
memory, an extra address line (A16) is provided (see the example
in Figure 57). The four regions are configured independently.
Table 147. Memory Regions
Address Start
Address End
Contents
0x10000000
0x1000FFFF
External Memory 0
0x20000000
0x2000FFFF
External Memory 1
0x30000000
0x3000FFFF
External Memory 2
0x40000000
0x4000FFFF
External Memory 3
Each external memory region can be controlled through three
MMRs: XMCFG, XMxCON, and XMxPAR.
0
912
3-
039
LATCH
ADuC7126
AD15:AD0
A16
EEPROM
64k × 16-BIT
A0:A15
D0:D15
CS
RAM
128k × 8-BIT
A0:A15
A16
D0:D7
CS
WE
OE
WE
OE
AE
MS0
MS1
WS
RS
Figure 57. Interfacing to External EEPROM/RAM
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