參數(shù)資料
型號(hào): ADUC7126BSTZ126-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 64/108頁(yè)
文件大?。?/td> 0K
描述: IC MCU 16/32B 126KB FLASH 80LQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲(chǔ)器容量: 126KB(63K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 80-LQFP
包裝: 帶卷 (TR)
Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 59 of 108
Table 79. GPxCON Registers
Name
Address
Default Value
Access
GP0CON
0xFFFFF400
0x00000000
R/W
GP1CON
0xFFFFF404
0x00000000
R/W
GP2CON
0xFFFFF408
0x00000000
R/W
GP3CON
0xFFFFF40C
0x00000000
R/W
GP4CON
0xFFFFF410
0x00000000
R/W
GPxCON are the Port x control registers that select the function
of each pin of Port x, as described in Table 80.
Table 80. GPxCON MMR Bit Descriptions
Bit
Description
[31:30]
Reserved.
[29:28]
Select function of Px.7 pin.
[27:26]
Reserved.
[25:24]
Select function of Px.6 pin.
[23:22]
Reserved.
[21:20]
Select function of Px.5 pin.
[19:18]
Reserved.
[17:16]
Select function of Px.4 pin.
[15:14]
Reserved.
[13:12]
Select function of Px.3 pin.
[11:10]
Reserved.
[9:8]
Select function of Px.2 pin.
[7:6]
Reserved.
[5:4]
Select function of Px.1 pin.
[3:2]
Reserved.
[1:0]
Select function of Px.0 pin.
Table 81. GPxPAR Registers
Name
Address
Default Value
Access
GP0PAR
0xFFFFF42C
0x20000000
R/W
GP1PAR
0xFFFFF43C
0x00000000
R/W
GP2PAR
0xFFFFF44C
0x000000FF
R/W
GP3PAR
0xFFFFF45C
0x00222222
R/W
GP4PAR
0xFFFFF46C
0x00000000
R/W
The GPxPAR registers program the parameters for Port 0, Port 1,
Port 2, Port 3, and Port 4. Note that the GPxDAT MMR must
always be written after changing the GPxPAR MMR.
Table 82. GPxPAR MMR Bit Descriptions
Bit
Description
31
Reserved.
[30:29]
Drive strength Px.7.
28
Pull-up disable Px.7.
27
Reserved.
[26:25]
Drive strength Px.6.
24
Pull-up disable Px.6.
23
Reserved.
[22:21]
Drive strength Px.5.
20
Pull-up disable Px.5.
19
Reserved.
[18:17]
Drive strength Px.4.
Bit
Description
16
Pull-up disable Px.4.
15
Reserved.
[14:13]
Drive strength Px.3.
12
Pull-up disable Px.3.
11
Reserved.
[10:9]
Drive strength Px.2.
8
Pull-up disable Px.2.
7
Reserved.
[6:5]
Drive strength Px.1.
4
Pull-up disable Px.1.
3
Reserved.
[2:1]
Drive strength Px.0.
0
Pull-up disable Px.0.
Table 83. GPIO Drive Strength Control Bits Descriptions
Control Bits Value
Description
00
Medium drive strength.
01
Low drive strength.
1x
High drive strength.
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
–24
–18
–12
–6
0
6
12
18
24
SINK/SOURCE CURRENT (mA)
SU
PP
LY
V
O
LT
A
G
E
(V)
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
09
123
-14
8
Figure 46. Programmable Strength for High Level
–0.4
–0.3
–0.2
–0.1
0.1
0
0.2
0.3
0.4
0.5
–24
–18
–12
–6
0
6
12
18
24
SINK/SOURCE CURRENT (mA)
SU
P
LY
VOL
TA
G
E
(V
)
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
09
12
3-
14
9
Figure 47. Programmable Strength for Low Level
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