參數(shù)資料
型號： UDA1352HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： 48 kHz IEC 60958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù)： 53/64頁
文件大?。?/td> 262K
代理商： UDA1352HL
2003 Mar 25
53
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
16 TIMING CHARACTERISTICS
V
DDD
= V
DDA
= 2.4 to 3.6 V; T
amb
=
40 to +85
°
C; R
L
= 5 k
; all voltages measured with respect to ground; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Device reset
t
rst
PLL lock time
reset active time
250
μ
s
t
lock
time-to-lock
f
s
= 32.0 kHz
f
s
= 44.1 kHz
f
s
= 48.0 kHz
85.0
63.0
60.0
ms
ms
ms
Serial interface input/output data timing
(see Fig.17)
I
2
S-bus bit clock input frequency
f
BCKI
1
T
cy(BCKI)
;
note 1
1
T
cy(BCKO)
;
note 1
128f
s
Hz
f
BCKO
I
2
S-bus bit clock output frequency
64f
s
64f
s
64f
s
Hz
t
BCKH
t
BCKL
t
r
t
f
t
su(WS)
t
h(WS)
t
su(DATAI)
t
h(DATAI)
t
h(DATAO)
t
d(DATAO-BCK)
data output to bit clock delay
t
d(DATAO-WS)
data output to word select delay
L3-bus microcontroller interface
(see Figs 18 and 19)
bit clock HIGH time
bit clock LOW time
rise time
fall time
word select set-up time
word select hold time
data input set-up time
data input hold time
data output hold time
30
30
10
10
10
10
0
20
20
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
cy(CLK)(L3)
t
CLK(L3)H
t
CLK(L3)L
t
su(L3)A
t
h(L3)A
t
su(L3)D
t
h(L3)D
t
(stp)(L3)
t
su(L3)DA
L3CLOCK cycle time
L3CLOCK HIGH time
L3CLOCK LOW time
L3MODE set-up time in address mode
L3MODE hold time in address mode
L3MODE set-up time in data transfer mode
L3MODE hold time in data transfer mode
L3MODE stop time in data transfer mode
L3DATA set-up time in address and data transfer
mode
L3DATA hold time in address and data transfer mode
L3DATA delay time in data transfer mode
L3DATA disable time for read data
500
250
250
190
190
190
190
190
190
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
h(L3)DA
t
d(L3)D
t
dis(L3)R
30
0
0
ns
ns
ns
50
50
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