參數(shù)資料
型號： UDA1352HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： 48 kHz IEC 60958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù)： 43/64頁
文件大?。?/td> 262K
代理商： UDA1352HL
2003 Mar 25
43
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
12.11 PLL coarse ratio (write)
Table 50
Register address 62H
Table 51
Description of register bits
Table 52
Coarse ratio setting for PLL, notes 1 and 2.
Notes
1.
In frequency synthesizer mode (mode 8), combinations of input frequency (f
i
), PR and CR as given in Table 53 are
supported. In all other modes, CR[15:0] must be set to the default value 0300H.
In frequency synthesizer mode (mode 8), EV2 (bit 10 in register address 40H) must be set to logic 1.
2.
Table 53
Possible combinations of f
i
, Pre-scaler Ratio (PR) and Course Ratio (CR)
BIT
15
14
13
12
11
10
9
8
Symbol
Default
CR15
0
CR14
0
CR13
0
CR12
0
CR11
0
CR10
0
CR9
1
CR8
1
BIT
7
6
5
4
3
2
1
0
Symbol
Default
CR7
0
CR6
0
CR5
0
CR4
0
CR3
0
CR2
0
CR1
0
CR0
0
BIT
SYMBOL
DESCRIPTION
15 to 0
CR[15:0]
Coarse ratio setting for PLL.
A 16-bit value to program the coarse ratio for the PLL in
mode 8. Default setting 0300H; see Table 52.
CR15 to CR0
COARSE RATIO
CR15
×
2
15
+ ... + CR15
×
2
0
f
i
(kHz)
12000
12000
12000
12000
12000
12000
12288
12288
12288
12288
12288
12288
PR
CR
WS FREQUENCY (kHz)
1/625
1/625
1/625
1/625
1/625
1/625
1/640
1/640
1/640
1/640
1/640
1/640
320
441
882
1280
1764
1920
320
441
882
1280
1764
1920
8000
11025
22050
32000
44100
48000
8000
11025
22050
32000
44100
48000
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