參數(shù)資料
型號： UDA1352HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： 48 kHz IEC 60958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù)： 35/64頁
文件大小： 262K
代理商： UDA1352HL
2003 Mar 25
35
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
12.4
Power-down settings (write)
Table 30
Register address 03H
Table 31
Description of register bits
BIT
15
14
13
12
11
10
9
8
Symbol
Default
PON_XTAL
0
BIT
7
6
5
4
3
2
1
0
Symbol
PON_
SPDIFIN
1
EN_INT
PONDAC
Default
1
1
BIT
SYMBOL
DESCRIPTION
15 to 13
12
reserved
Crystal oscillator operation.
A 1-bit value. When set to logic 0, the crystal oscillator is
disabled. When set to logic 1, the crystal oscillator is enabled. Default value is logic 0.
reserved
Power control SPDIF input.
A 1-bit value. When logic 0, power to the IEC 60958 bit
slicer is disabled. When set to logic 1, the power is enabled. Default value is logic 1.
reserved
Interpolator clock control.
A 1-bit value. When set to logic 0, the interpolator clock is
disabled. When set to logic 1, the interpolator clock is enabled. Default value is logic 1.
Power control DAC.
A 1-bit value to switch the DAC into power-on or power-down
mode. When set to logic 0, the DAC is in power-down mode. When set to logic 1, the
DAC is in power-on mode. Default value is logic 1.
PON_XTAL
11 to 5
4
PON_SPDIFIN
3 to 2
1
EN_INT
0
PONDAC
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