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參數(shù)資料
| 型號： | UDA1352HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 48 kHz IEC 60958 audio DAC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 32/64頁 |
| 文件大小： | 262K |
| 代理商： | UDA1352HL |
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2003 Mar 25
32
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
12.1
Clock settings (write)
Table 20
Register address 00H
Table 21
Description of register bits
Note
1.
These bits cannot be read.
Table 22
Crystal clock divider ratio settings
BIT
15
14
13
12
11
10
9
8
Symbol
Default
XTAL_DIV1 XTAL_DIV0
0
0
BIT
7
6
5
4
3
2
1
0
Symbol
XRATIO1
XRATIO0
CLKOUT_
SEL
FREQ_
SYNTH0
Default
0
0
0
0
BIT
SYMBOL
DESCRIPTION
15 to 10
9 to 8
reserved
Crystal clock divider ratio settings.
A 2-bit value to set the division ratio
between the internal crystal oscillator frequency and the DAC sampling
frequency in crystal operation mode (DAC clock is fixed at 64f
s
). Default value
is 00; note 1. See Table 22 for alternative values.
reserved
Pre-scaler ratio settings.
A 2-bit value to set the pre-scaler ratio in frequency
synthesizer mode (FREQ_SYNTH0 is logic 1). Default value is 00, see Table 23.
Clock output select.
A 1-bit value. When set to logic 1, the internal crystal
oscillator signal is used as the clock signal and is also available from
pin CLKOUT. When set to logic 0, the clock signal is recovered from the SPDIF
or WSI input signal. Default value is logic 0.
Frequency synthesizer mode.
A 1-bit value. When set to logic 1, frequency
synthesizer mode is enabled. When set to logic 0, the frequency synthesizer
mode is disabled. Default value is logic 0.
XTAL_DIV[1:0]
7 to 4
3 to 2
XRATIO[1:0]
1
CLKOUT_SEL
0
FREQ_SYNTH0
XTAL_DIV1
XTAL_DIV0
CRYSTAL CLOCK AND RATIO
0
0
1
1
0
1
0
1
128f
s
; ratio 1:2 (default)
256f
s
; ratio 1:4
384f
s
; ratio 1:6
512f
s
; ratio 1:8
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| UDA1352TS/N3112 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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