參數(shù)資料
型號: UDA1352HL
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: 48 kHz IEC 60958 audio DAC
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù): 22/64頁
文件大?。?/td> 262K
代理商: UDA1352HL
2003 Mar 25
22
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
10.3
Byte transfer
Each byte (8 bits) is transferred with the MSB first
(see Table 10).
Table 10
Byte transfer
10.4
Data transfer
A device generating a message is a transmitter, a device
receiving a message is the receiver. The device that
controls the message is the master and the devices which
are controlled by the master are the slaves.
10.5
Start and stop conditions
Both data and clock lines will remain HIGH when the bus
is not busy. A HIGH-to-LOW transition of the data line,
while the clock is HIGH, is defined as a start condition (S);
see Fig.9. A LOW-to-HIGH transition of the data line while
the clock is HIGH is defined as a stop condition (P).
MSB
BIT NUMBER
LSB
7
6
5
4
3
2
1
0
handbook, full pagewidth
MBC622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
Fig.9 START and STOP conditions on the I
2
C-bus.
10.6
Acknowledgment
There is no limit to the number of data bits transferred from
the transmitter to receiver between the start and stop
conditions. Each byte of eight bits is followed by one
acknowledge bit (see Fig.10). At the acknowledge bit, the
data line is released by the master and the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after receiving each byte. Also a master
must generate an acknowledge after receiving each byte
that has been clocked out of the slave transmitter.
The acknowledging device must pull-down the SDA line
during the HIGH period of the acknowledge clock pulse so
that the SDA line is stable LOW. Set-up and hold times
must be taken into account. A master receiver must signal
an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data
line HIGH to enable the master to generate a stop
condition.
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