參數(shù)資料
型號： UDA1352HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： 48 kHz IEC 60958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù)： 41/64頁
文件大小： 262K
代理商： UDA1352HL
2003 Mar 25
41
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
12.9
SPDIF input settings (write)
Table 46
Register address 30H
Table 47
Description of register bits
BIT
15
14
13
12
11
10
9
8
Symbol
Default
BIT
7
6
5
4
3
2
1
0
Symbol
COMBINE_
PCM
1
BURST_
DET_EN
1
SLICE_
SEL
0
Default
0
BIT
SYMBOL
DESCRIPTION
15 to 4
3
COMBINE_PCM
reserved
Combine PCM detection to lock indicator.
A 1-bit value to combine the PCM
detection status with the SPDIF and PLL lock indicator. When set to logic 0, the
lock indicator does not include PCM detection status. When set to logic 1, the
PCM detection status is combined with the lock indicator. Default value 1.
Burst preamble settings.
A 1-bit value to enable auto mute when burst
preambles are detected. When set to logic 0, muting is disabled. When set to
logic 1, muting is enabled; the output is muted when preambles are detected.
Default value 1.
When writing new settings via the L3-bus or I
2
C-bus interfaces, this bit should
stay at logic 0 (default value) to guarantee correct operation.
Slicer input selection.
A 1-bit value to select an IEC 60958 input signal.
When set to logic 0, the input signal is from pin SPDIF0. When set to logic 1,
the input signal is from pin SPDIF1. Default value 0.
2
BURST_
DET_EN
1
0
SLICE_SEL
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