參數(shù)資料
型號(hào)： UDA1352HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： 48 kHz IEC 60958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁(yè)數(shù)： 12/64頁(yè)
文件大?。?/td> 262K
代理商： UDA1352HL
2003 Mar 25
12
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
8.2
Clock regeneration and lock detection
The UDA1352HL has an on-board PLL for regenerating a
system clock from the IEC 60958 input bitstream.
Remark:
If there is no input signal, the PLL generates a
minimum frequency and the output spectrum shifts
accordingly. Since the analog output does not have an
analog mute, this means noise that is out of band under
normal conditions can move into the audio band.
When the on-board clock locks to the incoming frequency,
the PLL lock indicator bit is set and can be read via the
L3-bus or I
2
C-bus interfaces.
By default, PLL lock status and PCM detection status
indicator signals are internally combined. Pin LOCK goes
HIGH when the IEC 60958 decoder and the on-board
clock are both locked to the incoming bitstream and if the
incoming bitstream data is PCM. However, if the IC is
locked but the incoming signal is not PCM data, or it is
burst preamble, pin LOCK goes LOW. The combined lock
andPCMdetectionstatuscanbeoverriddenbytheL3-bus
or I
2
C-bus register bit settings.
Thelock indicationoutputsignalcanbeused,forexample,
for muting purposes. It can be used to drive an external
analog muting circuit to prevent out of band noise from
becoming audible when the PLL runs at its minimum
frequency (e.g. when there is no SPDIF input signal).
When valid PCM data is detected in the incoming
bitstream, pin PCMDET goes HIGH.
8.3
Crystal oscillator
The UDA1352HL uses an on-board crystal oscillator to
generate a clock signal. The clock signal can be used as
the internal clock, and is used directly by the DAC in
modes 6 and 7. This clock signal can also be output at
pin OSCOUT and can be applied to the SPDIF inputs.
By setting the UDA1352HL as a frequency synthesizer
(mode 8), a set of frequencies can be obtained, as shown
in Table 53.
8.4
Mute
The UDA1352HL uses a cosine roll-off mute in the DSP
data path part of the DAC. Muting the DAC (by pin MUTE
or via bit MT in L3-bus or I
2
C-bus modes), results in a soft
mute,asshowninFig.3.Thecosineroll-offsoftmutetakes
23 ms corresponding to 32
×
32 samples at a sampling
frequency of 44.1 kHz.
When operating in either the L3-bus or I
2
C-bus mode, the
device will mute the audio output on start-up by default.
Muting in these modes can only be disabled by setting
bit MT in the device register to logic 0.
A logic 1 on pin MUTE will always mute the audio output
signal in either the L3-bus or I
2
C-bus mode, or static pin
mode. This is in contrast to the UDA1350 and the
UDA1351 in which pin MUTE has no effect in the L3-bus
mode.
handbook, halfpage
mute
factor
0
10
5
15
25
0
0.8
MGU119
20
0.6
0.4
0.2
t (ms)
Fig.3 Mute as a function of raised cosine roll-off.
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