參數(shù)資料
型號(hào)： UDA1352HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： 48 kHz IEC 60958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁(yè)數(shù)： 23/64頁(yè)
文件大?。?/td> 262K
代理商： UDA1352HL
2003 Mar 25
23
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
handbook, full pagewidth
MBC602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
Fig.10 Acknowledge on the I
2
C-bus.
10.7
Device address
Before any data is transmitted on the I
2
C-bus, the target
device is always addressed first after the start procedure.
The target device is addressed using one byte having one
of four addresses set by pins DA0 and DA1.
The UDA1352HL acts as a slave receiver or a slave
transmitter. Therefore, the clock signal SCL is only an
input signal and the data signal SDA is bidirectional.
The UDA1352HL device address is shown in Table 11.
Table 11
I
2
C-bus device address
10.8
Register address
The register addresses in the I
2
C-bus mode are the same
as those in the L3-bus mode.
10.9
Write and read data
The I
2
C-bus configuration for a write and read cycle are
shown in Tables 12 and 13, respectively. The write cycle
writes pairs of bytes to the internal registers for the digital
sound feature control and system setting. These register
locations can also be read for device status information.
DEVICE ADDRESS
R/W
0/1
A6
1
A5
0
A4
0
A3
1
A2
1
A1
DA1
A0
DA0
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