參數(shù)資料
型號： UDA1352HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： 48 kHz IEC 60958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù)： 33/64頁
文件大小： 262K
代理商： UDA1352HL
2003 Mar 25
33
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
Table 23
Pre-scaler ratio settings
12.2
I
2
S-bus output settings (write)
Table 24
Register address 01H
Table 25
Description of register bits
Table 26
Digital data output formats
XRATIO1
XRATIO0
PRE-SCALER RATIO
0
0
1
1
0
1
0
1
1:36 (default)
1:625
1:640
1:1125
BIT
15
14
13
12
11
10
9
8
Symbol
Default
MUTEBP
0
BIT
7
6
5
4
3
2
1
0
Symbol
Default
SFORO2
0
SFORO1
0
SFORO0
0
BIT
SYMBOL
DESCRIPTION
15 to 9
8
MUTEBP
reserved
Mute bypass setting.
A 1-bit value. When set to logic 1, the mute bypass
setting is enabled; in out-of-lock situations or when non-PCM data is detected,
the output data is not muted. When set to logic 0, the output is muted in
out-of-lock situations. Default value is logic 0.
reserved
Digital data output formats.
A 3-bit value to set the digital output format.
Default value 000; see Table 26.
7 to 3
2 to 0
SFORO[2:0]
SFORO2
SFORO1
SFORO0
FORMAT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I
2
S-bus (default)
LSB-justified, 16 bits
LSB-justified, 18 bits
LSB-justified, 20 bits
LSB-justified, 24 bits
MSB-justified
reserved
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