參數(shù)資料
型號: UDA1352HL
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: 48 kHz IEC 60958 audio DAC
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù): 24/64頁
文件大?。?/td> 262K
代理商: UDA1352HL
2
2
P
P
4
U
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10.10 Write cycle
The write cycle is used to write data to the internal registers. The device and register addresses are one byte each, the setting data is always two bytes.
The I
2
C-bus configuration for a write cycle is shown in Table 12.
The write cycle format is as follows:
1.
The microcontroller begins by asserting a start condition (S).
2.
The first byte (8 bits) contains the device address ‘1001 110’ and the R/W bit is set to logic 0 (write).
3.
The UDA1352HL asserts an acknowledge (A).
4.
The microcontroller writes the 8-bit address (ADDR) of the UDA1352HL register to which data will be written.
5.
The UDA1352HL acknowledges (A) this register address.
6.
The microcontroller sends two bytes of data with the Most Significant (MS) byte first followed by the Least Significant (LS) byte; after each byte the
UDA1352HL asserts an acknowledge.
7.
After every pair of bytes that are transmitted, the register address is auto incremented; after each byte the UDA1352HL asserts an acknowledge.
8.
The UDA1352HL frees the I
2
C-bus allowing the microcontroller to generate a stop condition (P).
Table 12
Master transmitter writes to the UDA1352HL registers in I
2
C-bus mode.
Note
1.
Auto increment of register address.
DEVICE
ADDRESS
R/W
REGISTER
ADDRESS
DATA 1
DATA 2
(1)
DATA n
(1)
S
1001 110
0
A
ADDR
A
MS1
A
LS1
A
MS2
A
LS2
A
MSn
A
LSn
A
P
acknowledge from UDA1352HL
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