參數(shù)資料
型號(hào): TVP3026-175M
廠商: Texas Instruments, Inc.
英文描述: Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述: 視頻接口調(diào)色板Exract(組合像素模式視頻接口調(diào)色器)
文件頁(yè)數(shù): 66/107頁(yè)
文件大?。?/td> 707K
代理商: TVP3026-175M
3–6
3.6 Switching Characteristics (See Figures 3-1 and 3-2)
PARAMETER
TVP3026-135
MIN
TYP
TVP3026-175
MIN
TYP
UNIT
MAX
MAX
SCLK/RCLK frequency (see Note 7)
85
85
MHz
VCLK frequency (see Note 7)
85
85
MHz
ten1
tdis1
tv1
td1
Enable time, RD low to D(7–0) valid
40
40
ns
Disable time, RD high to D(7–0) disabled
17
17
ns
Valid time, D(7–0) valid after RD high
5
5
ns
Delay time, RD low to D(7–0) starting to turn on
5
5
ns
td2
Delay time, selected input clock high/low to
DOTCLK (internal signal) high/low
7
7
ns
td3
Delay time, SCLK high/low to RCLK high/low
(see Notes 8, 9, and 10)
1
2
4
1
2
4
ns
td6
tr
Analog output settling time(seeNote 11)
6
5
ns
Analog output rise time (see Note 12)
2
2
ns
Analog output skew
7. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and
90% levels is less than 4 ns (typically 3 ns). RCLK and VCLK can drive output capacitive loads up to 15 pF,
with worst-case transition times between 10% and 90% levels less than 4 ns (typically 3 ns).
8. The SCLK delay time to RCLK depends on the load that the signals drive. This parameter is measured with
a VCLK = RCLK load of 15 pF and SCLK load of 60 pF.
9. In SCLK mode, RCLK is delayed from SCLK so that when RCLK is connected to LCLK, the timing is
essentially the same as the TLC3407x family of parts.
10. This parameter applies when SCLK is used.
11. Measured within
±
1 LSB from 50% point of full-scale transition to output settling, (settling time does not
include clock and data feedthrough).
12. Measured between 10% and 90% of full-scale transition.
0
2
0
2
ns
NOTES:
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