參數(shù)資料
型號： TVP3026-175M
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器）
文件頁數(shù)： 12/107頁
文件大?。?/td> 707K
代理商： TVP3026-175M
1–6
1.5
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
76
FS ADJUST
I
Full-scale adjustment. A resistor connected between FS ADJUST and GND
controls the full-scale range of the DACs.
GND
17, 41, 46,
66, 69, 71,
73, 75,
81–83, 85,
118, 136,
159
Ground. All GND terminals must be connected. A common ground plane should
be used.
HSYNCOUT,
VSYNCOUT
67, 68
O
Horizontal and vertical sync outputs. These outputs are pipeline delayed
versions of the selected sync inputs. Output polarity inversion may be
independently selected using general control register bits GCR(1,0).
Analog current outputs. These outputs can drive a 37.5-
load directly (doubly
terminated 75-
line), thus eliminating the requirement for any external buffering.
IOR, IOG,
IOB
70, 72, 74
O
GI/O4– I/O0
58–62
I/O
Software programmable general I/O terminals that can be used to control
external devices.
LCLK
123
I
Latch clock input. LCLK latches pixel-bus-input data and system video controls.
VGA data may also be latched with LCLK when selected. LCLK may be a delayed
version of RCLK provided that linear phase changes in RCLK cause
corresponding linear phase changes in LCLK.
MCLK
121
O
Memory clock output. MCLK is the output of an independently programmable
PLL frequency synthesizer. The frequency range is 14 – 100 MHz. The dot clock
may be output on this terminal while the MCLK frequency is reprogrammed. See
subsection 2.4.2.1, Changing the MCLK Frequency
PCLKOUT
144
O
Pixel clock PLL output. PCLKOUT is a buffered version of the pixel clock PLL
output and is mainly for test purposes. This output is independent of the dot clock
source selected by the clock selection register.
PLLGND
142
Ground for PLL supplies. Decoupling capacitors should be connected between
PLLVDD and PLLGND. PLLGND should be connected to the system ground
through a ferrite bead.
PLLVDD
143, 146
PLL power supply. PLLVDD must be a well regulated 5-V power supply voltage.
Decoupling capacitors should be connected between PLLVDD and PLLGND.
Terminal 143 supplies power to the pixel clock PLL. Terminal 146 supplies power
to the MCLK PLL and the loop clock PLL.
OVS
96
I
Overscan input. OVS controls the display of custom screen borders. When OVS
is not used, it should be connected to GND.
ODD/EVEN
122
I
Odd or even field display. ODD/EVEN indicates odd or even field during
interlaced display for cursor operation. A low signal indicates the even field and
a high signal indicates the odd field. See subsection 2.7.4, Interlaced Cursor
Operation for cursor operation in interlace mode.
PLLSEL0,
PLLSEL1
1, 160
I
Pixel clock PLL frequency selection. PLLSELx selects among two fixed
frequencies and the programmed frequency of the pixel clock PLL.
NOTE 1: All unused inputs should be tied to a logic level and not allowed to float.
相關(guān)PDF資料
PDF描述
TVP3026-220 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
TVP3026-250 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
TX24 60.8 MM 5 X 8 DOT MATRIX DISPLAYS
TXB0102DCTR 2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR WITH AUTO DIRECTION SENSING AND 【15-kV ESD PROTECTION
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3026-175MDN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026-175MHFG 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026-175MHFGB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026-175PCE 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3026-220AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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