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參數(shù)資料
| 型號(hào)： | TVP3026-175M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 26/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-175M |
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2–12
6.
Disable the pixel clock PLL (PLLEN bit = 0). Program the pixel clock PLL N, M, and P registers
(with PLLEN bit = 1) for the original operating pixel frequency. Poll the pixel clock PLL status until
the LOCK bit is set to 1.
2.4.3
Loop Clock PLL
Many of the current high performance graphics accelerators with built in VGA support prefer to generate
their own VRAM shift clock and pixel data latching clock (LCLK) as discussed in subsection 2.5.2,
Frame-Buffer Timing Without Using SCLK As stated before, the TVP3026 provides an RCLK timing
reference output to be used by the graphics controller to generate these signals. A common industry
problem exists, however, in that the delay through the loop (i.e., from RCLK through the controller to produce
LCLK and pixel data) may be greater than the RCLK cycle time minus setup time. It then becomes very
difficult to resynchronize the rising edges of the LCLK signal to the internal dot clock within the specified
timing requirements. Variations in graphics accelerator propagation delays from device to device can cause
severe production problems at the board level. The TVP3026 incorporates a unique loop clock PLL circuit
to maintain a valid LCLK/dot clock phase relationship and ensure that proper LCLK and pixel data setup
timing is met, regardless of the amount of system loop delay.
After device reset, the loop clock PLL provides the dot clock frequency to the RCLK output multiplexer.
However, the RCLK output multiplexer will ignore the loop clock PLL output and instead pass the pixel clock
PLL output to the RCLK terminal, which provides a reference clock to the VGA controller. In this configuration
(VGA mode 2), the VGA controller returns VGA data and video controls along with a synchronous clock that
becomes the TVP3026 dot clock source using CLK0. The PLLSEL(1,0) lines select either the 25.057 MHz
or 28.636 MHz VGA frequencies.
Figure 2–2 illustrates the pixel data latching structure and the operation of the loop clock PLL. The selected
clock source generates the dot clock which drives most of the digital logic of the TVP3026. The dot clock
is used as a reference frequency by the loop clock PLL and is subdivided as specified by the N value register.
The incoming LCLK is used as the other input of the PLL and is subdivided as specified by the M value
register. The PLL generates RCLK with the proper frequency and phase shift to phase align the divided dot
clock and divided LCLK. The pixel bus is latched on the rising edge of LCLK and then aligned with the internal
dot clock to synchronize with internal logic.
Loop Clock
PLL
D Q
D Q
LCLK
Dot Clock
Generator
Dot
Clock
Input Data Latch Structure
TVP3026
RCLK
CLKx
LCLK
P(63–0)
Graphics
Accelerator
VRAM
From Pixel Clock PLL
Figure 2–2. Loop Clock PLL Operation
The bit assignments of the N-, M-, and P-value and the status register for the loop clock PLL are shown in
Table 2–14. The bits shown as 0 or set to 1 must be written with these fixed values. When cleared to 0,
PLLEN disables the PLL and when set to 1, enables the PLL to oscillate. When reset to 1,the LOCK status
bit indicates that the PLL has locked to the selected frequency. The remaining status register bits are for
test purposes.
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| TVP3026-250 | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-175MDN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026-175MHFG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026-175MHFGB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026-175PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-220AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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