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| 型號： | TVP3026-175M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 56/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-175M |
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2–42
2.15 Register Definitions
2.15.1
General-Control Register (Index: 0x1D, Access: R/W, Default: 0x00)
The general-control register definition is listed in Table 2–26.
Table 2–26. General-Control Register
BIT
NAME
VALUES
DESCRIPTION
GCR7
0
Reserved
GCR6
0: Disable (default)
Overscan enable. GCR6 specifies whether to enable the user-defined
Overscan enable. GCR6 specifies whether to enable the user defined
overscan screen border.
1: Enable
GCR5
0: Disable (default)
Sync enable. Bit GCR5 specifies whether sync information is to be output onto
IOG.
1: Enable
GCR4
0: 0 IRE (default)
Pedestal control. GCR4 specifies whether a 0 or 7.5 IRE blanking pedestal is
to be generated on the video outputs.
1: 7.5 IRE
GCR3
0: Little-endian (default)
Little-endian/big-endian select. GCR3 selects either little- or big-endian format
Little endian/big endian select. GCR3 selects either little or big endian format
for the pixel-bus interface.
1: Big-endian
GCR2
0
Reserved
GCR1
0: Do not invert (default)
VSYNCOUT output polarity. GCR1 specifies whether vertical sync output is
positive or negative.
1: Invert
GCR0
0: Do not invert (default)
1: Invert (high)
HSYNCOUT output polarity. GCR0 specifies whether horizontal sync output
is positive or negative.
2.15.2
The miscellaneous-control register definition is listed in Table 2–27.
Miscellaneous-Control Register (Index: 0x1E, Access: R/W, Default: 0x00)
Table 2–27. Miscellaneous-Control Register
BIT
NAME
VALUES
DESCRIPTION (SEE NOTE 9)
MSC7
0
Reserved
MSC6
0
Reserved
MSC5
0: True function
(default)
PSEL polarity select. When MSC5 is reset to 0 and setting PSEL to active high
selects direct-color (provided that the color-key function is set to select
direct-color) When MSC5 is set to 1 and then PSEL high selects pseudo-color or
direct-color). When MSC5 is set to 1, and then PSEL high selects pseudo-color or
true-color.
1: Complementary
MSC4
0: Disable (default)
Port select switching enable. When MSC4 is set to 1, direct-color/true-color or
direct-color/overlay switching is controlled by the PSEL input MSC5 controls the
direct-color/overlay switching is controlled by the PSEL input. MSC5 controls the
polarity of the PSEL input.
1: Enable
MSC3
0: 6-bit (default)
8- or 6-bit operation bit. When MSC2 is set to 1, MSCR3 determines 8- or 6-bit
8 or 6 bit operation bit. When MSC2 is set to 1, MSCR3 determines 8 or 6 bit
operation.
1: 8-bit
MSC2
0: Enable (default)
8/6 terminal disable. When MSC2 is set to 1, the 8/6 terminal is ignored and the
8/6 function is controlled by bit 3 of this register.
1: Disable
MSC1
0
Reserved
MSC0
0: Disable (default)
1: Enable
DAC power down When MSC0 is set to 1 the DACs power down
DAC power down. When MSC0 is set to 1, the DACs power down.
NOTE 9: Additional power reduction can be achieved by disabling the internal dot clock by writing the binary value 110
to clock selection register (index: 0x1A) bits 2–0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TVP3026-175MDN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026-175MHFG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026-175MHFGB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026-175PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-220AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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