參數(shù)資料
型號(hào)： TVP3026-175M
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器）
文件頁(yè)數(shù)： 36/107頁(yè)
文件大?。?/td> 707K
代理商： TVP3026-175M
2–22
The first active pixel bus load (LCLK rising edge) of the horizontal line must load the first word
of the M-word sequence comprising the pixel group. For designs not using SCLK
(bit TCR5 = 0), the first active pixel bus load coincides with the first time SYSBL is sampled high.
For designs using SCLK (bit TCR5 = 1), the first active pixel bus load occurs two LCLKs after the
first time SYSBL is sampled high. See Figures 2–5 and 2–6.
Synchronization of the packed-24 operation is performed by the loop clock PLL. Consider an N:M packed-24
mode which packs N pixels into M pixel bus words. Internally, the TVP3026 must run through a sequence
of N dot clocks for each pixel group. The loop clock PLL supplies a clock (RCLK) which is M/N times the
dot clock frequency. The graphics accelerator uses RCLK to generate SYSBL. Initially, SYSBL could change
on any of the M LCLKs of the sequence. Once SYSBL is sampled, the TVP3026 declares the proper LCLK
as the first in the M-word sequence. However, the relationship between LCLK and the internal dot clock has
not been established. Only one LCLK rising edge in the M-word pixel group is aligned with the internal dot
clock, but which one of the M LCLKs is aligned has not been specified. This selection is important for
operation of the unpacking logic and is programmable using the LCLK edge synchronizer delay. The LCLK
edge synchronizer function allows selection of which LCLK edge of the pixel group is aligned with the internal
dot clock. For each packed-24 mode, there is an optimum setting for LES1 and LES0 (see Tables 2–14 and
2–15).
The following steps outline a typical setup procedure for packed-24 mode:
1.
Program the pixel clock PLL for the desired dot clock frequency and poll status until locked.
2.
Select pixel clock PLL as clock source in clock selection register.
3.
Program true-color control register and multiplex control register as given in Table 2–17.
4.
Download palette RAM when gamma correction is being used (true-color mode).
5.
Program latch control register as given in Table 2–27.
6.
Set port select and color-key switching functions appropriately. For true-color mode, select the
palette RAM. This is the power-up default. For direct-color mode, select palette bypass. From
defaults, this can be done by setting bit MSC5 = 1 in the miscellaneous control register.
7.
Select loop clock PLL for output on RCLK terminal by setting MCLK/loop clock control register
bit MKC5 to 1.
8.
Program the loop clock PLL as described in subsection 2.4.3.2, Programming for Packed-24
Modes and poll status until locked.
相關(guān)PDF資料
PDF描述
TVP3026-220 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
TVP3026-250 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
TX24 60.8 MM 5 X 8 DOT MATRIX DISPLAYS
TXB0102DCTR 2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR WITH AUTO DIRECTION SENSING AND 【15-kV ESD PROTECTION
TXB0102DCTT 2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR WITH AUTO DIRECTION SENSING AND 【15-kV ESD PROTECTION
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3026-175MDN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026-175MHFG 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026-175MHFGB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026-175PCE 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3026-220AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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