參數(shù)資料
型號: TVP3026-175M
廠商: Texas Instruments, Inc.
英文描述: Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述: 視頻接口調(diào)色板Exract(組合像素模式視頻接口調(diào)色器)
文件頁數(shù): 15/107頁
文件大小: 707K
代理商: TVP3026-175M
2–1
2 Detailed Description
2.1
Microprocessor Unit Interface
The standard microprocessor unit (MPU) interface is supported, giving the MPU direct access to the
registers and memories of the TVP3026. The processor interface is controlled using read and write strobes
(RD, WR), four register select terminals (RS3–RS0), the D7–D0 data terminals, and the 8/6-select terminal.
The 8/6 terminal is used to select between an 8- or 6-bit-wide data path to the color palette RAM and is
provided to maintain compatibility with the IMSG176. See subsection 2.1.1, 8/6 Operation
Table 2–1 lists the direct register map. These registers are addressed directly by the register select lines
RS0–RS3. Table 2–2 lists the indirect register map. The index for the indirect register map is loaded into
the index register (direct register: 0000). This register also stores the palette RAM write address and cursor
RAM write address. The indexed data register (direct register: 1010) is then used to read or write the register
pointed to in the indirect register map. The index does not post-increment following accesses to the indirect
map.
Table 2–1. Direct Register Map
RS3
RS2
RS1
RS0
REGISTER ADDRESSED BY MPU
R/W
DEFAULT (HEX)
0
0
0
0
Palette/Cursor RAM Write Address/
Index Register
R/W
XX
0
0
0
1
Palette RAM Data
R/W
XX
0
0
1
0
Pixel Read-Mask
R/W
FF
0
0
1
1
Palette/Cursor RAM Read Address
R/W
XX
0
1
0
0
Cursor/Overscan Color Write Address
R/W
XX
0
1
0
1
Cursor/Overscan Color Data
R/W
XX
0
1
1
0
Reserved
0
1
1
1
Cursor/Overscan Color Read Address
R/W
XX
1
0
0
0
Reserved
1
0
0
1
Direct Cursor Control
R/W
00
1
0
1
0
Indexed Data
R/W
XX
1
0
1
1
Cursor RAM Data
R/W
XX
1
1
0
0
Cursor-Position X LSB
R/W
XX
1
1
0
1
Cursor-Position X MSB
R/W
XX
1
1
1
0
Cursor-Position Y LSB
R/W
XX
1
1
1
1
Cursor-Position Y MSB
R/W
XX
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