參數(shù)資料
型號: TVP3026-175M
廠商: Texas Instruments, Inc.
英文描述: Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述: 視頻接口調(diào)色板Exract(組合像素模式視頻接口調(diào)色器)
文件頁數(shù): 32/107頁
文件大?。?/td> 707K
代理商: TVP3026-175M
2–18
SYSBL
LCLK = RCLK
P(63–0)
SCLK
Latch SYSBL
Falling Edge
Latch First Group of Pixel Data
1st
Group
2nd
Group
3rd
Group
Last Group
Last Group of Pixel Data
Latch SYSBL
Rising Edge
Latch Last Group
of Pixel Data
Latch Last Group
of Pixel Data
Figure 2–6. Frame-Buffer Timing Using SCLK
2.5.4
When SCLK is used, the TVP3026 supports the special clocking requirements of some VRAM devices. For
example, some VRAM devices require the first SCLK pulse to occur during blanking (SYSBL active)
between the split shift register transfer (SSRT) and the full shift register transfer VRAM operations. When
SCLK mode is enabled (TCR5 = 1) and SYSBL is active, a high pulse on the SFLAG input is passed directly
to the SCLK output. When the high pulse on SFLAG is detected at any time during blanking, the first SCLK
pulse normally generated after coming out of blanking is suppressed. This is because the SSRT operation
leaves the first pixel group of the new line on the pixel bus as opposed to the last pixel group of the previous
line. Figure 2–7 shows the SCLK timing mode with the first SCLK pulse relocated. When this function is not
used, the SFLAG terminal should be connected to GND.
Split Shift-Register-Transfer Support
SYSBL
LCLK = RCLK
SCLK
Latch First Group
of Pixel Data
Last
Group
2nd
Group
3rd
Group
4th
Group
1st Group
SCLK Between Split Shift Register and Full Shift Register Transfer
Latch Last Group of Pixel Data
SFLAG
P(63–0)
Figure 2–7. Frame-Buffer Timing Using SCLK (With First SCLK Pulse Relocated)
相關(guān)PDF資料
PDF描述
TVP3026-220 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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