參數(shù)資料
型號： TVP3026-175M
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器）
文件頁數(shù)： 29/107頁
文件大?。?/td> 707K
代理商： TVP3026-175M
2–15
The latch-control register definition is listed in Table 2–16.
Table 2–16. Latch-Control Register (Index: 0x0F, Access: R/W, Default: 0x06)
BIT NAME
VALUES
DESCRIPTION
LCR7, LCR6
00
0
×
06
Reserved
LCR5 LCR0
LCR5–LCR0
All 1:1, 4:1, 8:1, and 16:1 multiplex modes.
0
×
07
All 2:1 multiplex modes.
8:3 packed-24 or
4:3 packed-24 (revision A)
0
×
08
0
×
20
0
×
1F
0
×
1E
0
×
1C
0
×
18
4:3 packed-24 (revision B)
5:2 packed-24
5:4 packed-24,
×
1 horizontal zoom
5:4 packed-24,
×
2 horizontal zoom
5:4 packed-24,
×
4 horizontal zoom
5:4 packed-24,
×
8 horizontal zoom
The P and Q frequency dividers must be programmed so that the VCO is within its operating range of 110
MHz to 220 MHz. The VCO frequency is post scaled by the P-divider followed by the Q-divider. The P-divider
register (P) can take on values of 0, 1, 2, or 3 which correspond to division factors of 1, 2, 4, or 8. The
Q-divider register (Q) is stored in bits 2 – 0 of the MCLK/loop clock control register (index: 0x39) and can
take on values of 0, 1, 2, . . ., 7 which correspond to division factors of 2, 4, 6, . . ., 16. The total post-scalar
frequency division factor is:
F
VCO
F
D
Next, set F
VCO
to the lower limit of 110 MHz and solve for Z:
Z
F
D
Z
2
P
1
(Q
1)
K
65
65
N
M
(9)
110
K
65
65
N
M
(10)
Finally, determine the P and Q values:
IF Z
16 then P
TRUNC log
2
Z , Q
3, Q
0
IF Z
16 then P
INT
Z
16
16
1
Set bits 7–2 of the P-value register to 1111 10. This enables the PLL to oscillate and enables the LCLK edge
synchronizer function. To reset the PLL, clear bit 7 of the P-value register to 0.
2.4.3.3
After reset, the TVP3026 defaults to VGA mode 2 (VGA pass through mode, see subsection 2.6.2, VGA
Modes) as do other devices in the TVP302x family. The RCLK terminal outputs the pixel clock PLL frequency
which is selected by PLLSEL1 and PLLSEL0. CLK0 is selected as the clock source and the VGA port is
selected as well as VGABL, VGAHS, and VGAVS and these are latched with CLK0. The MCLK PLL outputs
the default 50.11 MHz clock frequency.
Typical Device Connection
Figure 2–3 shows the typical device connection for a system with VRAM clocked by the graphics
accelerator. After power up, the pixel clock PLL is output on RCLK and this clock drives the graphics
accelerator’s VGA controller and video timing logic. The accelerator’s output clock is output synchronous
to the VGA data and is input to the TVP3026 CLK0 input as the dot clock source.
相關(guān)PDF資料
PDF描述
TVP3026-220 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
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