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參數(shù)資料
| 型號： | TVP3026-175M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 53/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-175M |
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2–39
2.11.4
Silicon Revision
The silicon revision register (index: 0x01) is a read-only register that enables software to identify the silicon
revision of the TVP3026. On the first pass silicon, this register reads back 0x00. A major revision number
is stored in bits 7–4 and a minor revision number is stored in bits 3–0.
2.12 General-Purpose I/O Register and Terminals
The general-purpose I/O register and output terminals provide a means of controlling external functions
through the TVP3026 microinterface. The 8-bit general-purpose I/O data register has five bit locations
(D0–D4) tied to external I/O terminals (GI/O0–GI/O4). The other three bits (D5–D7) can be used for
general data storage and do not affect any other circuitry. The general-purpose I/O data register is controlled
by the general-purpose I/O control register. GP I/O control register bits IOC0–IOC4 control whether the
corresponding general-purpose I/O terminals are configured as inputs or outputs. The reset default
condition is for GP I/O control register bits IOC0–IOC4 = 0, which configures terminals GI/O0–GI/O4 as
inputs. When any of the GP I/O control register bits are set to 1, the corresponding GI/O terminals are
configured as outputs.
The general-purpose I/O control register, data register, and terminal relationships are shown in Table 2–25.
Table 2–25. General Purpose I/O Registers
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
General-Purpose I/O Control Register
Index: 0x2A
Access: R/W
Default: 0x00
X
X
X
IOC4
IOC3
IOC2
IOC1
IOC0
General-Purpose I/O Data Register
Index: 0x2B
Access: R/W
Default: Uninitialized
X
X
X
D4
D3
D2
D1
D0
General-Purpose I/O Terminal Locations
X = do not care
GI/O4
GI/O3
GI/O2
GI/O1
GI/O0
2.13 Reset
There are two ways to reset the TVP3026. The RESET input terminal can perform a hardware reset.
Alternatively, the device has an integrated software reset function.
A hardware reset is initiated by pulling the RESET input terminal low. When RESET is pulled low all
TVP3026 registers go to default states. This reset is asynchronous, and any glitch on this terminal could
change the intended register setup. The default state at reset is VGA mode, and all default register settings
are given in Table 2–2. When a reset is desired at power up, an external resistor, capacitor, and diode
network can be connected to the RESET terminal. When TTL logic is employed to provide the signal to the
RESET terminal, a pullup resistor should be used to make sure that CMOS levels are achieved.
For a software reset, anytime the reset register (index: 0xFF) is written to, all registers are initialized to
TVP3026 default settings. The data written into the reset register is ignored.
2.14 Analog Output Specifications
The DAC outputs are controlled by three current sources (only two for IOR and IOB) as shown in
Figure 2–12. The default condition is to have 0 IRE difference between blank and black levels, which is
shown in Figure 2–13. When a 7.5-IRE (Institute of Radio Engineers, predecessor to the IEEE) pedestal
is desired, it can be selected by setting bit 4 of the general-control register. This video output is shown in
Figure 2–14.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-175MDN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026-175MHFG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026-175MHFGB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026-175PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-220AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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