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參數(shù)資料
| 型號(hào)： | TVP3026-175M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 25/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-175M |
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2–11
Table 2–13. MCLK/Loop Clock Control Register (Index: 0x39 hex, Access: R/W, Default: 0x18)
BIT NAME
VALUES
DESCRIPTION
MKC7
0
Reserved
MKC6,
MKC5
00: Pixel clock PLL
(default)
01: Loop clock PLL
10: Dot clock /N
11: Reserved
Selects signal to output on RCLK terminal. Pixel clock PLL is selected as
default to support VGA mode 2. In VGA mode 2, the graphics accelerator
receives RCLK and returns its VGA output clock to the CLK0 terminal
along with synchronous VGA data. Select loop clock PLL for all modes
using LCLK data latching. The dot clock /N option provides the output of
the loop clock PLL N prescaler. This signal is a low pulse, one dot clock
wide, with a repetition rate of FREF / (65–N).
MKC4 selects the signal to output on MCLK terminal. MCLK PLL is
selected as default. Select dot clock to ensure a stable output on MCLK
while MCLK PLL frequency is reprogrammed. See subsection 2.4.2.1,
Changing the MCLK Frequency A change of this bit does not take effect
until MKC3 bit transitions from 0 to 1. During this transistion, the MKC4
bit should not be changed.
MKC4
0: Dot clock
1: MCLK PLL (default)
MKC3
0:
1: (default)
Strobe for MCLK terminal output multiplexer control (MKC4). A 0 to 1
transition of this bit strobes in bit MKC4, causing bit MKC4 to take effect.
While MKC3 is transitioning from 0 to 1, MKC4 should not be changed.
MKC2, MKC1,
MKC0
000: Divide by 2 (default)
001: Divide by 4
010: Divide by 6
011: Divide by 8
100: Divide by 10
101: Divide by 12
110: Divide by 14
111: Divide by 16
Loop clock PLL post scalar Q divider. This additional frequency division
is applied after the 2P division of the loop clock PLL P-value register. For
a binary value of Q in MKC2–MKC0, the resulting frequency division is
2*(Q+1).
After the device resets, the MCLK PLL outputs a 50.11 MHz clock frequency and the pixel clock PLL output
depends on the PLLSEL1 and PLLSEL0 inputs according to Table 2–11. These frequencies assume a
standard 14.31818 MHz crystal reference. The actual output frequencies are proportional to the reference
frequency used.
2.4.2.1
Changing the MCLK Frequency
The MCLK is normally used as the graphics controller system clock and memory clock. During
reprogramming of the PLLs, a wide range of unpredictable frequencies are generated as the PLL transitions
to the new programmed frequency. These transition effects can produce unwanted results in some systems.
The TVP3026 provides a mechanism for smooth transitioning of the MCLK PLL. The following programming
steps are recommended.
1.
Disable the pixel clock PLL (PLLEN bit = 0). Program the pixel clock PLL N, M, and P registers
(with PLLEN bit = 1) to the same frequency to which MCLK is to be changed. Poll the pixel clock
PLL status until the LOCK bit is set to 1.
2.
Select the pixel clock PLL as the dot clock source if it is not already selected.
3.
Switch to output dot clock on the MCLK terminal by writing bits MKC4 and MKC3 to 0,0 followed
by 0,1 in the MCLK/loop clock control register.
4.
Disable the MCLK PLL (PLLEN bit = 0). program the MCLK PLL N, M, and P registers (with
PLLEN bit = 1) for the new frequency. Poll the MCLK PLL status until the LOCK bit is set to 1.
5.
Switch to output MCLK on the MCLK terminal by writing bits MKC4 MKC3 to 1,0 respectively,
followed by 1,1 respectively in the MCLK/loop clock control register.
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