![](http://datasheet.mmic.net.cn/370000/TVP3026-135_datasheet_16743199/TVP3026-135_18.png)
2–4
2.1.4
The registers for the three cursor colors and the overscan border color are accessed through the direct
register map. See Section 2.9, Overscan Borderdescription and subsection 2.7.3, Three-Color 64 X 64
Cursor for use of the cursor colors.
Cursor and Overscan Color Registers
The color write address register (direct register: 0100) must be initialized before writing to the color registers.
The lower two bits of this register select one of the four color registers according to Table 2–4. The selected
24-bit color register is loaded a byte at a time by writing a sequence of three bytes (red, green, and blue)
to the color data register (direct register: 0101). After the blue byte is written, the color address register
increments to the next color. All four colors may be loaded with a single write to the color write address
register followed by 12 consecutive writes to the color data register.
The color read address register (direct register: 0111) must be initialized before reading from the color
registers. The lower two bits of this register select one of the four color registers according to Table 2–4. Next,
the color data register (direct register: 0101) is read three times, producing red, green, and blue bytes from
the selected register. After the blue byte is read, the color address register is incremented to the next color.
All four colors may be read with a single write to the color read address register followed by 12 consecutive
reads of the color data register.
The sequence followed by the color address register is overscan color, cursor color 0, cursor color 1, cursor
color 2, . . ., etc. The starting point depends on what was written to the color write address or color read
address register.
Table 2–4. Color Register Address Format
BIT 1
BIT 0
REGISTER
0
0
Overscan color
0
1
Cursor color 0
1
0
Cursor color 1
1
1
Cursor color 2
2.2
The color-palette RAM is addressed by an internal 8-bit address register for reading/writing data from/to the
RAM. This register is automatically incremented following a RAM transfer, allowing the entire palette to be
read/written with only one access of the address register. When the address register increments beyond
the last location in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM
are asynchronous to the internal clocks but are performed within one dot clock. Therefore, read/write
accesses do not cause any noticeable disturbance on the display.
Color-Palette RAM
The color palette RAM is 24 bits wide for each location and 8 bits wide for each color. Since a MPU access
is 8 bits wide, the color data stored in the palette is eight bits when the 6-bit mode is chosen. When the 6-bit
mode is chosen, the two MSBs of color data in the palette have the values previously written. However, when
they are read back in the 6-bit mode, the two MSBs are zeros to be compatible with INMOS IMSG176 and
Brooktree Bt176. The output multiplexer shifts the six LSB bits to the six MSB positions and fills the two LSBs
with 0s after the color palette. The multiplexer then feeds the data to the DAC. The test mode data register
and the cyclic redundancy check (CRC) calculation both take data after the output multiplexer, enabling total
system verification. The color palette access is described in the following two sections, and it is fully
compatible with IMSG176/8 and Bt476/8.