參數(shù)資料
型號(hào)： TVP3026-175M
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器）
文件頁(yè)數(shù)： 30/107頁(yè)
文件大?。?/td> 707K
代理商： TVP3026-175M
2–16
Figure 2–4 shows the typical device connection for a system with VRAM clocked by the TVP3026. In this
case, the RCLK is tied back to the LCLK and this same clock drives the graphics-accelerator VGA controller
and video timing logic. If necessary, the RCLK and SCLK signals may be externally buffered within the timing
constraints (RCLK to LCLK delay) of the TVP3026. The pixel clock PLL is output on RCLK after power up.
For high resolution modes in both configurations, the pixel data is received from VRAM and the loop clock
PLL is used to adjust RCLK so that the received LCLK is aligned with the internal dot clock. The loop clock
PLL must be selected for output on the RCLK terminal. The pixel clock PLL (or an external clock source)
should be selected as the dot clock source.
Graphics
Accelerator
VRAM
VGA(7–0)
LCLK
CLK0
P(63–0)
MCLK
RCLK
TVP3026
Figure 2–3. Typical Configuration – VRAM Clocked by Accelerator
Graphics
Accelerator
VRAM
VGA(7–0)
LCLK
CLK0
P(63–0)
MCLK
RCLK
TVP3026
SCLK
Figure 2–4. Typical Configuration – VRAM Clocked by TVP3026
2.5
Frame-Buffer Interface
The TVP3026 provides two output clock signals and one input clock signal for controlling the frame-buffer
interface — SCLK, RCLK, and LCLK. The VCLK output is a division of the internal dot clock and has no
guaranteed phase relationship with RCLK. Therefore, VCLK should not be used for frame buffer interface
timing (pixel data and video controls). VCLK can drive general purpose external logic. Clocking of the frame
buffer interface is discussed in subsection 2.5.1, Frame-Buffer Clocking The 64-bit pixel bus allows many
operational display modes as defined in Section 2.6, Multiplexing Modes of Operation and Table 2–17. The
pixel latching sequence is initiated by a rising edge on LCLK. For those multiplexed modes in which multiple
pixels are latched on one LCLK rising edge, the pixel clock shifts the pixels out starting with the pixels that
reside on the low numbered pixel port terminals. For example, in an 8-bit-per-pixel pseudo-color mode with
an 8:1 multiplex ratio, the pixel display sequence is P(7–0), P(15–8), P(23–16), P(31–24), P(39–32),
P(47–40), P(55–48), and P(63–56).
The TVP3026 frame-buffer interface also supports little- and big-endian data formats on the pixel bus. This
can be controlled by general-control register (GCR) bit 3. See subsection 2.6.1, Little-Endian and
Big-Endian Data Format for details of operation.
相關(guān)PDF資料
PDF描述
TVP3026-220 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
TVP3026-250 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
TX24 60.8 MM 5 X 8 DOT MATRIX DISPLAYS
TXB0102DCTR 2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR WITH AUTO DIRECTION SENSING AND 【15-kV ESD PROTECTION
TXB0102DCTT 2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR WITH AUTO DIRECTION SENSING AND 【15-kV ESD PROTECTION
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3026-175MDN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026-175MHFG 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026-175MHFGB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026-175PCE 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3026-220AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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