參數(shù)資料
型號(hào)： TMX320C6201
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP)
中文描述： 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器）
文件頁(yè)數(shù)： 60/72頁(yè)
文件大小： 1552K
代理商： TMX320C6201
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
60
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupt response cycles
An external-interrupt event is triggered once by a high pulse on an INTx signal. If, on one rising edge of the
CLKOUT1, the INTx is recognized as low and on the next CLKOUT1 rising edge the INTx is recognized as high,
an external interrupt is detected. As early as three cycles later, the IACK signal can pulse for one cycle with the
number of the active interrupt encoded on the four INUM lines. The IACK and INUM signals indicate the start
of any interrupt processing, not just for external interrupts. The INUM identification number reflects the relative
bit position of the processed interrupt within the interrupt flag register (IFR). Also, one cycle prior to the IACK
pulse, all instructions (except branch delay slots, which delay IACK) that have not reached the execution stage
are annulled and the address of the annulled instruction closest to execution stage is saved in the appropriate
interrupt return pointer (IRP or NRP). The instructions that already have begun executing complete the
remaining execution stages while the reset service fetch packet is being fetched and decoded. During the seven
fetch/decode cycles the processor does not start processing any new instructions (hence the seven cycle
interrupt overhead). The interrupt service fetch packet starts executing on the seventh cycle following IACK (see
Figure 40).
timing requirements for the interrupt response cycle
NO
MIN
MAX
UNIT
4
tw(INTR)
tw(ILOW)
tsu(IHIGH-CKH)
Pulse duration, width of the interrupt pulse
1
cycle
5
Pulse duration, width of the low state preceding interrupt pulse
1
cycle
6
Setup time, INTx low before CLKOUT1 high
0.3
ns
switching characteristics for the interrupt response cycle
NO
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
1
tr(IACK)
Response time, IACK high after INTx low
3
cycles
2
tw(IDEAD)
Pulse duration, width of the interrupt overhead
(no instructions executed)
7
7
cycles
3
tr(ISFP)
Response time, interrupt service fetch packet execution
after INTX low
9
cycles
7
th(CKH-ILOW)
td(CKH-IACK)
td(CKH-INUM)
Hold time, INTx low after CLKOUT1 high
3.0
ns
8
Delay time, CLKOUT1 high to IACK valid
1
ns
9
Delay time, CLKOUT1 high to INUM valid
1
ns
P
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