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參數(shù)資料
| 型號： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數(shù)字信號處理器） |
| 文件頁數(shù)： | 17/72頁 |
| 文件大?。?/td> | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
CPU registers (continued)
Table 2 lists the instructions associated with the CPU functional units.
Table 2. Instruction Set Summary
FUNCTION UNITS
.L UNIT
.M UNIT
.S UNIT
.D UNIT
ABS
ADD
AND
CMPEQ
CMPGT
CMPGTU
CMPLT
CMPLTU
LMBD
MV
NEG
.S2 only
.D2 only
NORM
NOT
OR
SADD
SAT
SSUB
SUB
SUBC
XOR
ZERO
MPY
SMPY
ADD
ADDK
ADD2
AND
B disp
B IRP
B NRP
B reg
CLR
EXT
EXTU
MVC
MV
MVK
MVKH
NEG
NOT
OR
SET
SHL
SHR
SHRU
SSHL
STP
SUB
SUB2
XOR
ZERO
ADD
ADDA
LD mem
LD mem (15-bit offset)
MV
NEG
ST mem
ST mem (15-bit offset)
SUB
SUBA
ZERO
Table 3 lists each pipeline phase and the phase descriptions. The pipeline-stage symbols shown can be used
to interpret the instruction-execute phases shown in Table 4.
Table 3. Pipeline Description
PIPELINE PHASE
PIPELINE STAGE
SYMBOL
DURING THIS PHASE:
Program Fetch
Program Address Generate
Program Address Send
Program Wait
Program Data Receive
PG
PS
PW
PR
Address of the fetch packet is determined.
Address of the fetch packet is sent to memory.
Program memory read is performed.
Fetch packet is expected at CPU boundary.
Program Decode
Execute Packet Dispatch
Decode
DP
DC
Next execute packet is sent to functional units.
Instructions are decoded in functional units.
Execute
Execute 1
E1
Instruction conditions are evaluated, operands read.
Load/store addresses are computed/modified.
Branches affect fetch packet in PG stage.
Single-cycle results are written to register file.
Execute 2
E2
Load address is sent to memory.
Store/STP address and data are sent to memory.
Single-cycyle instructions can set the SAT bit.
Multiply results are written to the register file.
Load memory reads continue.
Multi-cycle instruction can set the SAT bit.
Execute 3
E3
Execute 4
Execute 5
E4
E5
Load data arrives at the CPU boundary.
Load data is placed in the register.
Table 4 shows the delay slots and execute stages used by the ’C6201.
P
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